Receiver Clock Phase Calibration During Live Data Sampling
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Solution Overview
Problem
High-speed serial receivers are sensitive to process variations, voltage drift, and temperature drift, leading to phase mismatch between clock signals, which affects their operation and data recovery accuracy.
Innovation Solution
A receiver with live clock phase calibration that includes a main DFE data sampler and an adaptive DFE data sampler, using a calibration process to align the phases of the clock signals during live data traffic by selectively adjusting the phases of the main and adaptive clock signals, ensuring accurate data recovery without interrupting the data stream.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If signaling rates are increased to improve data transmission speed, then productivity is improved, but the receiver becomes more sensitive to process variations, voltage drift, and temperature drift, worsening reliability
Solution Approach 1:
The patent performs preliminary phase calibration of the clock signal before data sampling occurs. A calibration circuit adjusts the phase of the clock signal in advance to compensate for expected variations, ensuring that the main sampler and adaptive sampler are properly synchronized before they begin their respective sampling operations. This preliminary adjustment prevents phase mismatch from degrading performance at high signaling rates.
Solution Approach 2:
The patent employs a feedback mechanism where the adaptive sampler's output is used to generate a correction signal that adjusts the phase of the clock signal. The system continuously monitors the phase relationship between clock signals and automatically corrects any drift by feeding back phase adjustment information to the clock generation circuitry, thereby maintaining synchronization despite process variations, voltage drift, or temperature changes.
2Measurement precision
If clock phase calibration is performed to align clock signals and improve data recovery accuracy, then measurement precision is improved, but the device complexity increases due to additional calibration circuits and control logic
Solution Approach 1:
The patent combines the calibration functionality with the existing adaptive equalization circuitry. The same sampler that performs adaptive sampling also generates the error signal used for phase calibration. By merging these functions, the patent avoids adding completely separate calibration hardware and instead utilizes existing circuit resources to achieve phase alignment, thereby reducing the increase in device complexity.
Solution Approach 2:
The calibration circuit is designed to serve multiple purposes: it calibrates the phase of the clock signal for both the main sampler and adaptive sampler, and it simultaneously provides equalization functionality. This multi-functional approach reduces the overall complexity by having a single circuit perform what would otherwise require multiple separate circuits.
3Reliability
If live calibration is performed during data traffic to maintain clock synchronization, then reliability is improved, but loss of time occurs due to calibration adjustments and phase alignment operations
Solution Approach 1:
The patent performs calibration continuously during normal data traffic operation rather than stopping data flow to perform calibration. The calibration circuit operates in parallel with the data sampling circuits, making real-time phase adjustments without interrupting the data stream. This continuous calibration approach maintains synchronization reliability while minimizing time loss by avoiding data transmission interruptions.
Solution Approach 2:
The patent applies small, incremental phase adjustments rather than large corrections. By making partial adjustments to the clock phase based on gradual drift detection, the system maintains synchronization with minimal disruption to data flow. This approach avoids the need for extensive calibration operations that would cause significant time loss.
Data Source
AI summary
A receiver with clock phase calibration is disclosed. A first sampling circuit generates first digital data based on an input signal, a sampling phase of the first sampling circuit controlled by a first clock signal. A second sampling circuit generates second digital data based on the input signal, a sampling phase of the second sampling circuit controlled by a second clock signal. Circuitry within the receiver calibrates the clocks in different stages. During a first calibration stage, a phase of the second clock signal is adjusted while the first digital data is selected for generating the output data. During a second calibration stage, a phase of the first clock signal is adjusted while the first digital data is selected for the output data path.