Receiver Clock Phase Initialization for Fast Timing Recovery
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Solution Overview
Problem
Existing clock recovery technologies in receivers, such as those used in high-speed serial communication and Gigabit Ethernet, face challenges in achieving fast convergence of timing recovery and equalization without increasing the operational frequency of the A/D converter, leading to potential delays in communication processes, especially in applications requiring deterministic timing.
Innovation Solution
A receiver configuration that includes an A/D converter, an equalizer, a timing recovery part, a detector, and an initial phase setting mechanism, where the detector sets the initial phase of the recovery clock based on a predetermined threshold and elapsed time, allowing for high-speed convergence without increasing the A/D converter's operational frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the phase of the recovery clock is linearly varied at a greatly slow speed in the open loop mode, then the convergence operation of the equalizer is not affected by the timing recovery part, but the convergence process takes long time
Solution Approach 1:
The patent applies preliminary action by detecting the signal start timing before the convergence process begins and setting the initial phase of the recovery clock based on this detected timing. This preliminary phase setting ensures that the timing recovery part and equalizer start their convergence operations simultaneously from an optimized initial state, rather than sequentially. The detector detects when the input signal transitions from no-signal state, and this timing information is used to initialize the phase of the recovery clock before the main convergence process starts.
2Reliability
If the timing recovery part and equalizer both deal with interface wave caused by inter-code interference, then they intrinsically affect each other, but the convergence process may sometimes take long time at the start
Solution Approach 1:
The patent implements feedback by using the detected signal start timing to adjust and set the initial phase of the recovery clock. The detector continuously monitors the input signal and provides feedback about the signal start timing to the initial phase setting mechanism. This feedback loop ensures that the timing recovery part's initial phase is optimally coordinated with the equalizer's convergence operation, allowing both parts to work together efficiently from the beginning rather than independently or sequentially.
Data Source
AI summary
A receiver includes: an A/D converter that performs an analog digital conversion of an input signal; an equalizer that equalizes an output from the A/D converter, eliminates inter code interference and obtains a data output; a timing recovery part that generates a recovery clock from the data output of the equalizer; a detector that detects the timing when an input signal varies from a no-signal state and has reached a predetermined threshold; and an initial phase setting part that sets as the initial phase of the recovery clock by the timing recovery part, a timing when the predetermined time has elapsed after the timing detected by the detector.