Receiver Clock Phase Offset for DFE Sampling Timing Error
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Solution Overview
Problem
In high-speed data communication systems, decision feedback equalizers fail to properly sample data due to un-cancelled inter-symbol interference (ISI), leading to errors in clock signal recovery and data sampling.
Innovation Solution
A receiver is designed to offset the in-phase clock signal by a phase offset responsive to the gain of the decision feedback equalizer, effectively advancing the clock signal to account for un-cancelled ISI, ensuring accurate sampling within the data eye.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If decision feedback equalizer is used for high-speed data communication, then inter-symbol interference is reduced, but intrinsic offset causes sampling timing error
Solution Approach 1:
The patent applies preliminary action by calculating the intrinsic offset value in advance based on DFE tap weights and applying this offset to the sampling clock signal before the sampling operation. The offset calculation is performed using the formula: offset = Σ(w_i × d_i) where w_i are the DFE tap weights and d_i are the data symbols. This pre-calculated offset is then used to adjust the sampling clock phase proactively, preventing the timing error from occurring during the actual sampling process.
Solution Approach 2:
The patent implements feedback by using the DFE equalization process itself to generate the offset information needed for clock adjustment. The same tap weights used for equalization are reused to calculate the intrinsic offset, creating a feedback loop where the equalization process informs the timing correction. This feedback mechanism ensures that the sampling clock is continuously adjusted based on the actual channel conditions and DFE operation.
2Reliability
If analog adder is used in decision feedback equalizer, then inter-symbol interference is cancelled, but varying delay is introduced to received data
Solution Approach 1:
The patent introduces an intermediary element - the intrinsic offset calculation mechanism - that mediates between the DFE equalization process and the sampling clock generation. Instead of directly modifying the analog signal path, the offset calculation serves as an intermediary that translates DFE tap weights into timing corrections. This intermediary approach allows the system to maintain the benefits of analog equalization while compensating for its timing side effects through a separate digital control path.
3Ease of operation
If in-phase clock signal is used for sampling, then data sampling is simplified, but sampling occurs too delayed due to un-cancelled ISI
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the phase parameter of the sampling clock signal based on the calculated intrinsic offset. The phase of the sampling clock is modified from its standard position to a corrected position that accounts for the DFE-induced delay. This parameter adjustment maintains the simplicity of in-phase sampling while correcting its timing inaccuracy, allowing the system to keep the easy-to-implement in-phase architecture without sacrificing sampling precision.
Data Source
AI summary
A receiver is provided that generates a data sampling clock that is offset by clock offset that is a function of a decision feedback equalizer gain to account for a data sampling timing error that would occur without the clock delay.