Receiver Clock Recovery Initial Phase for Fast Signal Startup
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Solution Overview
Problem
Existing clock recovery technologies in receivers, such as those used in high-speed serial communication and Gigabit Ethernet, face challenges in converging quickly at the start of a communication process, especially when the input signal transitions from a no-signal state, leading to potential delays due to slow phase variation of the recovery clock and dependency on the operational frequency of the A/D converter.
Innovation Solution
A receiver configuration that includes an A/D converter, an equalizer, a timing recovery part, a detector, and an initial phase setting part, where the detector sets the initial phase of the recovery clock based on a predetermined threshold and elapsed time, allowing for high-speed convergence without increasing the operational frequency of the A/D converter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the phase of the recovery clock is linearly varied at a greatly slow speed in the open loop mode, then the convergence operation of the equalizer is not affected by the timing recovery part, but the convergence time becomes excessively long and indeterminate
Solution Approach 1:
The patent applies preliminary action by detecting the transition from no-signal state to signal state in advance, and pre-setting the initial phase of the recovery clock based on this detection. This allows the timing recovery part to start with an optimized initial condition rather than gradually varying phase from zero, significantly reducing convergence time while maintaining reliability.
2Speed
If the operational frequency of the A/D converter is increased to achieve high-speed convergence, then the convergence speed improves, but the circuit configuration becomes complicated and circuit area increases
Solution Approach 1:
The patent changes the parameter of initial phase setting for the recovery clock based on the detected signal transition timing. By adjusting the initial phase parameter dynamically rather than increasing the A/D converter frequency, the system achieves high-speed convergence without complicating the circuit configuration or increasing power consumption.
3Reliability
If the timing recovery part and equalizer both operate in paths dealing with interference wave caused by inter-code interference, then they intrinsically affect each other, but the convergence process takes long time especially at the start
Solution Approach 1:
The patent applies preliminary action by having the timing recovery part detect the signal transition from no-signal state and pre-set the initial phase before the equalizer begins its convergence operation. This preliminary phase setting reduces the interference between the timing recovery part and equalizer, allowing both to converge faster without compromising interference elimination capability.
Data Source
AI summary
A receiver includes: an A/D converter that performs an analog digital conversion of an input signal; an equalizer that equalizes an output from the A/D converter, eliminates inter code interference and obtains a data output; a timing recovery part that generates a recovery clock from the data output of the equalizer; a detector that detects the timing when an input signal varies from a no-signal state and has reached a predetermined threshold; and an initial phase setting part that sets as the initial phase of the recovery clock by the timing recovery part, a timing when the predetermined time has elapsed after the timing detected by the detector.