Receiver Clock Recovery and DFE Without DAC Reference Voltage

Solution Overview

Problem

High-speed serial link receivers face challenges in miniaturization and power consumption due to the need for a digital-to-analog converter (DAC) to generate a reference voltage for adaptive equalization, which consumes a significant portion of the receiver's power and area, and the difficulty in accurately compensating for phase and intersymbol interference (ISI) without a separate reference voltage.

Innovation Solution

A receiver design that uses a 2UI integrator to integrate data signals over a two-unit interval, a sampling circuit to obtain integrated data, and an adaptive feedback circuit to adjust the phase of clock signals and equalize ISI without a reference voltage, reducing power consumption and enabling miniaturization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a DAC is used to generate reference voltage for adaptive equalization, then equalization performance is improved, but power consumption and area increase significantly

Engineering Contradiction:

Improveequalization performanceVSAvoidpower consumption

Core Design Contradiction:

Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent extracts and eliminates the DAC component from the receiver structure. Instead of using a DAC to generate reference voltage for adaptive equalization, the invention uses the integrated output signal directly from the integrator to perform equalization operations, thereby removing the power-consuming and area-intensive DAC while maintaining equalization performance

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The integrator output signal is made multi-functional by using it for both clock and data recovery operations and adaptive equalization simultaneously. This eliminates the need for separate reference voltage generation through a DAC, as the same integrated signal serves multiple purposes in the receiver

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Measurement precision

If a DAC is used to generate reference voltage for adaptive equalization, then equalization performance is improved, but device area increases

Engineering Contradiction:

Improveequalization performanceVSAvoidreceiver area

Core Design Contradiction:

Measurement precisionVSArea of stationary object

Solution Approach 1:

The patent extracts and eliminates the DAC component from the receiver structure. Instead of using a DAC to generate reference voltage for adaptive equalization, the invention uses the integrated output signal directly from the integrator to perform equalization operations, thereby removing the power-consuming and area-intensive DAC while maintaining equalization performance

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent merges the reference voltage generation function into the integrator output signal itself. The integrated signal that would traditionally require a separate DAC for reference voltage generation is now directly used for adaptive equalization, combining multiple functions into a single signal path and reducing overall receiver area

Inventive Principle:

Principle #5Merging (Combining)

3Measurement precision

If a separate reference voltage is used for adaptive equalization, then equalization accuracy is improved, but device complexity increases

Engineering Contradiction:

Improveequalization accuracyVSAvoidreceiver complexity

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The integrator output signal is made multi-functional by using it for both clock and data recovery operations and adaptive equalization simultaneously. This eliminates the need for separate reference voltage generation through a DAC, as the same integrated signal serves multiple purposes in the receiver

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The integrator output signal serves itself by providing the reference signal needed for adaptive equalization without requiring external DAC generation. The system uses its own integrated signal to perform equalization, eliminating the need for separate reference voltage generation circuitry

Inventive Principle:

Principle #25Self-service

Data Source

PatentUS20250385680A1Receiver performing clock and data recovery and adaptive equalization using integrator, and method of operating the same

Publication Date: 2025.12.18 UI (UNIVERSITY IND FOUNDATION) YONSEI UNIVERSITY

AI summary

The present disclosure provides a receiver capable of low power consumption and miniaturization and a method of operating the same. The receiver is capable of adaptively compensating the phase of a clock signal and ISI without using a reference voltage based on a pattern of data detected using an integrator, and a method of operating the same. The disclosed method is being performed in a receiver including a clock signal generation circuit, a 2UI integrator, a Decision Feedback Equalization (DFE), a sampling circuit, and an adaptive feedback circuit.