Source-Synchronous Receiver Clock Recovery for Jitter Margin
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Solution Overview
Problem
Source-synchronous receivers face challenges in accurately sampling data signals due to jitter in clocking signals, which affects timing margin and data integrity, especially in high-frequency double-data-rate systems.
Innovation Solution
A delay-locked loop configuration is implemented using an edge sampler and phase aligner to filter out jitter by aligning the phase-adjusted clocking signal with the received source-synchronous clocking signal, producing a receiver clocking signal that samples the data signal with maximum timing margin, and incorporating phase shifters and injection locked oscillators to further refine the timing alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional clocking methods are used in high-frequency double-data-rate systems, then data transmission speed is increased, but timing margin deteriorates due to jitter
Solution Approach 1:
The patent implements a delay-locked loop (DLL) that continuously monitors the phase relationship between the received clock signal and the sampling clock signal, and automatically adjusts the sampling clock phase to maintain optimal timing alignment. This feedback mechanism compensates for jitter and phase variations, preserving timing margin even at high data transmission speeds
Solution Approach 2:
The system dynamically adjusts the phase of the sampling clock signal in real-time based on the received clock signal characteristics. The delay element within the DLL provides variable delay control, allowing the sampling timing to adapt to changing clock conditions and maintain maximum timing margin throughout operation
2Productivity
If clock signal frequency is increased to achieve higher data rates, then productivity is improved, but jitter increases affecting sampling accuracy
Solution Approach 1:
The delay-locked loop continuously compares the phase of the received clock signal with the sampling clock signal and provides real-time feedback adjustment. This feedback mechanism tracks and compensates for jitter introduced by high-frequency clock signals, maintaining sampling accuracy despite increased data rates
Solution Approach 2:
The system performs preliminary phase alignment by capturing the received clock signal and using it to pre-adjust the sampling clock phase before actual data sampling occurs. This preliminary action ensures that sampling is always performed at the optimal point in the data eye, maintaining accuracy at high data rates
Data Source
AI summary
A source-synchronous clocking signal is sampled by an edge sampler triggered by a phase-adjusted version of the clocking signal. The output of the edge sampler is used as a phase-error indicator for a filtered feedback loop that aligns the phase-adjusted clocking signal to minimize, on average, the difference between the received source-synchronous clocking signal and the phase-adjusted version of the clocking signal minus the setup time of the sampler. This forms a delay-locked loop configuration. The phase adjustment information used to produce the aligned phase-adjusted clocking signal is then to produce a receiver clocking signal that is used to sample the source-synchronous data signal.