Receiver Clock Test Circuitry for Jitter Tolerance
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Solution Overview
Problem
Current systems for testing the jitter tolerance and frequency offset conditions of clock and data recovery (CDR) circuits in integrated circuits require high-precision test equipment, making it difficult to test devices outside of a controlled facility and limiting the accuracy of simulating high signaling rates.
Innovation Solution
The use of a peer lane CDR circuit to generate a test clock with controlled jitter and frequency offset conditions, allowing for precise simulation of timing variations within the CDR circuitry, enabling in-situ testing without the need for specialized equipment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If high-precision test equipment is used to generate test signals with controlled jitter, then measurement precision of jitter tolerance is improved, but device complexity and cost increase, and ease of operation decreases
Solution Approach 1:
The CDR circuit uses its own recovered clock signal to generate test patterns with controlled jitter by manipulating the feedback loop, eliminating the need for external high-precision test equipment. The circuit serves itself by using its internal resources (recovered clock, feedback path) to create the test conditions.
Solution Approach 2:
The patent introduces a test mode that acts as an intermediary between the CDR circuit and the external environment. In this mode, the CDR circuit generates test signals internally through controlled manipulation of its feedback loop, serving as an intermediary that eliminates the need for complex external equipment.
2Measurement precision
If high-precision test equipment is used to simulate jitter conditions, then measurement precision is improved, but ease of operation deteriorates as testing becomes limited to controlled facilities
Solution Approach 1:
The CDR circuit generates its own test signals with controlled jitter using its internal feedback loop and recovered clock, eliminating dependence on external high-precision equipment and specialized test facilities. The circuit can perform self-testing in various operating conditions.
Solution Approach 2:
The patent segments the testing function from the normal operation mode by introducing a separate test mode that can be activated when needed. This allows the CDR circuit to perform jitter tolerance testing independently without requiring external equipment or controlled facility environments.
3Measurement precision
If external test equipment is used to generate test signals, then measurement precision is improved, but loss of time increases due to equipment setup and calibration requirements
Solution Approach 1:
The CDR circuit generates test signals internally using its own recovered clock and feedback mechanisms, eliminating the need for external equipment setup and calibration. The test signals are generated directly within the circuit, significantly reducing preparation time.
Solution Approach 2:
The test capability is built into the CDR circuit during manufacturing, with all necessary test generation functions pre-configured within the circuit itself. This preliminary integration eliminates the need for time-consuming external equipment setup during actual testing.
Data Source
AI summary
An integrated circuit is operable in two modes, including a test mode in which a pattern of variation is injected into a receiver's sampling clock and used to simulate jitter. Adding frequency offset, jitter or both, to this clock can be equivalent to adding jitter of an equal magnitude but opposite sign in a transmitted test signal. In this way, a clock can be produced that simulates timing variations that can be encountered during mission function operation of the device under test, while test input data is applied by local pattern generators or other data sources that, under test conditions, do not, or need not, exhibit such variations. In detailed embodiments, these techniques can be separately employed in one or more clock and data recovery circuits (CDRs) of the integrated circuit; for example, a first local clock recovery circuit in a first receiver can be caused to produce a test clock which simulates a condition to be tested, and while a second receiver in the plurality of receivers that includes a second local clock recovery circuit is caused to use the test clock in place of the reference clock while receiving a test data sequence at its input.