High-Speed Receiver Compensation Circuits for Slicer Calibration

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Solution Overview

Problem

Existing receivers face challenges due to process variations in slicers, leading to incorrect or unintended results from analog-to-digital conversions.

Innovation Solution

A multi-purpose compensation circuit is introduced to adjust the analog front-end (AFE) output, incorporating transistors, adjustable current sources, and configurable resistance and capacitance components to calibrate and compensate for variations in slicers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If standard slicers are used without compensation circuits, then device complexity is reduced, but manufacturing precision deteriorates due to process variations causing incorrect conversion results

Engineering Contradiction:
Improveconversion accuracyVSAvoidcircuit complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The compensation circuits perform preliminary calibration actions before the actual analog-to-digital conversion process. The circuits pre-adjust for process variations by establishing correct reference voltage levels and compensating for mismatches in input pairs, ensuring that subsequent conversions are accurate without requiring complex post-processing or replacement of varied components

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The compensation circuits act as intermediary elements between the analog front end and the slicers. These intermediate circuits condition the signals by adjusting voltage levels, compensating for variations, and preparing the signals in a manner that accounts for slicer mismatches, thereby mediating the interface between components with inherent process variations

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If compensation circuits are added to adjust for slicer variations, then conversion accuracy is improved, but device complexity increases due to additional components

Engineering Contradiction:
Improvesignal measurement accuracyVSAvoidcircuit structure
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The compensation circuits achieve improved measurement precision by dynamically adjusting circuit parameters such as voltage levels, current values, and timing characteristics. The circuits modify these parameters based on detected variations in slicer performance, allowing accurate measurements despite process variations without requiring fundamentally different circuit topologies

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The compensation circuits incorporate feedback mechanisms that monitor the output of slicers and adjust compensation parameters accordingly. By continuously detecting measurement results and modifying compensation signals based on this feedback, the circuits maintain high measurement accuracy while using relatively simple additional circuitry rather than completely complex systems

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS20250150087A1Multi-purpose compensation circuits for high-speed receivers
Publication Date: 2025.05.08 SAMSUNG SDI CO LTD
  • US20250150087A1 patent drawing
  • US20250150087A1 patent drawing
  • US20250150087A1 patent drawing

AI summary

A device includes a first compensation circuit configured to adjust an analog front end (AFE) output to generate a first adjusted AFE output, a first data slicer configured to output a first voltage based on the first adjusted AFE output. The first compensation circuit includes a first path between a voltage source and a ground, including a first transistor, a first adjustable current source, a first input voltage node configured to receive the AFE output, and a first output voltage node coupled to the first data slicer, a second path between the voltage source and the ground, including a second transistor, a second adjustable current source, a second input voltage node configured to receive the AFE output, and a second output voltage node coupled to the second data slicer, and a configurable resistance resistor and a configurable capacitance capacitor coupled in parallel across the first path and the second path.