High-Speed Receiver Compensation Circuits for Slicer Mismatch

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Solution Overview

Problem

In receivers with analog front ends (AFE) coupled to data slicers, process variations during manufacturing lead to differences in slicer responses, resulting in incorrect or unintended results due to variations in transistor biases and common mode voltages, which existing technologies have not effectively addressed.

Innovation Solution

The implementation of a compensation circuit with adjustable current sources and configurable resistance and capacitance components across parallel paths, allowing for calibration of the AFE output to account for input pair mismatches and adjust the frequency response, thereby generating adjusted outputs that compensate for slicer variations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If process variations are accepted during manufacturing, then manufacturing precision is improved, but slicer response consistency deteriorates

Engineering Contradiction:
Improveslicer response consistencyVSAvoidmanufacturing process complexity
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent applies preliminary action by implementing compensation circuits that are pre-configured with adjustable components (resistors, capacitors, current sources) before final operation. These circuits are designed in advance to counteract the expected process variations, allowing slicers to be compensated for mismatches without requiring complex post-manufacturing adjustments or recalibrations.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If compensation circuits are added to each slicer, then slicer variation compensation is improved, but device complexity increases

Engineering Contradiction:
Improvesignal accuracyVSAvoidcircuit structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies parameter changes by utilizing adjustable electrical parameters (resistance, capacitance, current) within the compensation circuits. These parameters can be tuned to match the specific characteristics of each slicer, allowing for precise compensation of variations without requiring fundamentally different circuit architectures. The adjustable parameters enable fine-tuning of the compensation effect.

Inventive Principle:
Principle #35Parameter changes

3Adaptability or versatility

If adjustable current sources are implemented, then frequency response adjustment is improved, but manufacturing precision requirements increase

Engineering Contradiction:
Improvefrequency response tuningVSAvoidcomponent matching
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The patent applies dynamics by implementing adjustable and tunable components (variable resistors, capacitors, and current sources) that can be dynamically configured during manufacturing or operation. This dynamic adjustability allows the compensation circuits to be tailored to specific slicer characteristics, compensating for variations without requiring extremely tight initial component matching. The dynamic nature of the components provides flexibility in achieving the desired frequency response.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentEP4216441A1Multi-purpose compensation circuits for high-speed receivers
Publication Date: 2023.07.26 SAMSUNG DISPLAY CO LTD
  • EP4216441A1 patent drawingFigure 1
  • EP4216441A1 patent drawingFigure 2
  • EP4216441A1 patent drawingFigure 3~4

AI summary

A device includes a first compensation circuit configured to adjust an analog front end (AFE) output to generate a first adjusted AFE output, a first data slicer configured to output a first voltage based on the first adjusted AFE output. The first compensation circuit includes a first path between a voltage source and a ground, including a first transistor, a first adjustable current source, a first input voltage node configured to receive the AFE output, and a first output voltage node coupled to the first data slicer, a second path between the voltage source and the ground, including a second transistor, a second adjustable current source, a second input voltage node configured to receive the AFE output, and a second output voltage node coupled to the second data slicer, and a configurable resistance resistor and a configurable capacitance capacitor coupled in parallel across the first path and the second path.