Receiver DFE Calibration Using Shared Interpolation Logic
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Solution Overview
Problem
Existing memory systems face challenges in implementing separate Decision Feedback Equalization (DFE) values for each receiver due to process, voltage, and temperature variations, which impact accuracy and efficiency, and current solutions are costly in terms of power consumption and space when using multiple calibration circuits.
Innovation Solution
Implementing interpolation logic with calibration circuits to generate and store candidate voltage values for DFE, allowing each receiver to apply respective DFE values through interpolation or selection, improving reliability and read speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate calibration circuits are implemented for each receiver to enable independent DFE calibration, then receiver reliability and read accuracy are improved, but power consumption and space requirements increase significantly
Solution Approach 1:
The patent merges the calibration functionality into a shared calibration circuit that serves multiple receivers. The calibration circuit generates calibration data that is distributed to multiple receivers, allowing them to perform independent DFE calibration without requiring separate dedicated calibration circuits for each receiver. This consolidation reduces overall power consumption and space requirements while maintaining the ability to calibrate each receiver independently.
Solution Approach 2:
The calibration circuit is designed with multi-functionality to serve multiple receivers simultaneously. It can generate and distribute calibration data to different receivers based on their specific requirements, making a single circuit perform the work of multiple dedicated circuits. This universal approach reduces resource consumption while preserving receiver-specific calibration capabilities.
2Reliability
If separate calibration circuits are implemented for each receiver to enable independent DFE calibration, then receiver reliability and read accuracy are improved, but device complexity and space requirements increase
Solution Approach 1:
The patent consolidates calibration functionality into a single shared calibration circuit that serves multiple receivers. This merging approach reduces device complexity by eliminating the need for multiple separate calibration circuits, while still enabling each receiver to perform independent DFE calibration using the shared calibration data.
Solution Approach 2:
The calibration process is segmented into distinct phases: calibration data generation by the shared calibration circuit, distribution of calibration data to receivers, and actual DFE calibration execution at each receiver. This segmentation allows the complex calibration functionality to be distributed and managed efficiently, reducing overall device complexity while maintaining receiver-specific calibration capabilities.
3Device complexity
If traditional equalization methods are used without separate DFE calibration per receiver, then device complexity is reduced, but manufacturing precision and signal accuracy deteriorate due to PVT variations
Solution Approach 1:
The patent implements dynamic adjustment of DFE parameters based on calibration data that accounts for process, voltage, and temperature (PVT) variations. Each receiver uses its specific calibration data to adjust its DFE parameters, compensating for manufacturing variations and environmental conditions. This approach maintains signal accuracy without requiring overly complex hardware, as the precision is achieved through adaptive parameter adjustment rather than increased hardware complexity.
Data Source
AI summary
Methods, systems, and devices for receiver decision feedback equalization calibration are described. A memory system may support implementing respective decision feedback equalization (DFE) values at respective receivers using interpolation logic. For example, a calibration circuit may generate and store a quantity of candidate voltage values corresponding to the application of different DFE values at the receivers. The memory system may use the interpolation logic to generate (e.g., interpolate, generate) respective voltage values corresponding to a DFE value for application at a respective receiver based on the stored candidate voltage values. The interpolation logic may output the voltage values via a serial bus to each receiver, and each receiver may apply, to respectively received data, a DFE value corresponding to a respectively received voltage value.