Receiver and Divider Clocks for Low-Distortion Duty Cycle Control
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Solution Overview
Problem
Conventional duty cycle correction circuits for semiconductor memories are large and consume excessive power, making them undesirable for reducing duty cycle distortion in clock signals, which can lead to erroneous operations.
Innovation Solution
A semiconductor device with a receiver circuit and clock divider circuit that generates internal clocks with reduced duty cycle distortion by adjusting the voltage swing and phase relationships of clock signals, using current sources and variable resistances controlled by a dynamic duty cycle correction signal to minimize power consumption and area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional duty cycle correction circuits are used, then duty cycle distortion is corrected, but the circuit area and power consumption increase significantly
Solution Approach 1:
The duty cycle correction function is segmented into two parts: (1) a receiver circuit that generates clocks with reduced duty cycle distortion, and (2) a clock divider circuit that further reduces distortion. This segmentation allows each circuit to perform a simplified function, reducing overall area while maintaining correction effectiveness.
Solution Approach 2:
The receiver circuit inherently generates clocks with reduced duty cycle distortion through its differential signaling architecture and controlled impedance design, without requiring a separate dedicated duty cycle correction circuit. The clock divider circuit then further reduces distortion using simple delay matching, making the system self-correcting rather than requiring external correction hardware.
2Reliability
If conventional duty cycle correction circuits are used, then duty cycle distortion is corrected, but power consumption increases excessively
Solution Approach 1:
The power consumption is segmented and optimized across two stages: the receiver circuit uses differential signaling with controlled impedance to minimize distortion generation, and the clock divider circuit uses simple delay-matched paths to further reduce distortion. This segmentation avoids the high power consumption of conventional single-stage correction circuits by distributing the correction function across multiple low-power stages.
Solution Approach 2:
The receiver circuit inherently reduces duty cycle distortion through its differential architecture and impedance control, eliminating the need for power-hungry external correction circuits. The clock divider circuit then provides additional reduction using minimal power through delay matching, making the overall system power-efficient while maintaining correction effectiveness.
3Measurement precision
If clock timing accuracy is improved, then operational reliability increases, but circuit complexity increases
Solution Approach 1:
The timing accuracy improvement is achieved through segmented approaches: (1) the receiver circuit uses differential signaling and controlled impedance for inherent distortion reduction, and (2) the clock divider circuit uses delay-matched paths for further refinement. This segmentation achieves high timing accuracy without requiring a single complex correction circuit, thereby reducing overall device complexity.
Solution Approach 2:
The system achieves high timing accuracy through self-service mechanisms: the receiver circuit inherently generates low-distortion clocks via its differential architecture, and the clock divider circuit further refines timing through delay matching. This eliminates the need for complex external timing correction circuits, reducing device complexity while maintaining high timing accuracy.
Data Source
AI summary
Apparatuses and methods for duty cycle distortion correction of clocks are disclosed. An example apparatus includes a clock circuit configured to receive complementary input clocks and a control signal and to provide multiphase clocks responsive to complementary input clocks. The clock circuit is further configured to be in a first mode or second mode controlled by the control signal and configured to provide the multiphase clocks having greater duty cycle distortion in a first mode than in a second mode.