Receiver Equalizer Control for ISI Compensation and Clock Timing
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Solution Overview
Problem
Existing semiconductor integrated circuits face challenges in accurately compensating for signal losses due to transmission characteristics in high-speed serial communications, particularly in non-uniform transmission lines, which can lead to intersymbol interference (ISI) and affect data decoding precision.
Innovation Solution
A semiconductor integrated circuit with a digital receiver circuit that includes multiple equalizer circuits and control mechanisms to adjust tap coefficients, utilizing a combination of feed-forward equalizers (FFE) and decision feedback equalizers (DFE) to compensate for signal losses and synchronize clock signals, thereby improving timing adjustment precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single equalizer circuit is used for signal compensation, then the device complexity is reduced, but the timing adjustment precision and ability to handle non-uniform transmission lines deteriorates
Solution Approach 1:
The patent divides the equalizer into multiple independent equalizer circuits (first equalizer and second equalizer) with different tap coefficient adjustment mechanisms. The first equalizer uses a single control circuit for tap coefficient adjustment, while the second equalizer uses multiple control circuits, allowing independent optimization of timing and signal compensation without increasing overall system complexity
2Measurement precision
If multiple equalizer circuits with independent control are used, then the timing adjustment precision is improved, but the device complexity increases
Solution Approach 1:
The patent merges the control functions by making the second control circuit share the same physical structure as the first control circuit, while implementing different control methods. Both control circuits use identical hardware resources but apply different algorithms: the first control circuit adjusts tap coefficients based on signal strength, while the second control circuit adjusts tap coefficients based on timing error detection, thereby improving timing precision without proportionally increasing device complexity
3Ease of operation
If a fixed tap coefficient adjustment method is used, then the ease of operation is improved, but the adaptability to different transmission characteristics deteriorates
Solution Approach 1:
The patent implements dynamic adaptability through two distinct tap coefficient adjustment methods. The first equalizer uses automatic gain control to dynamically adjust tap coefficients based on received signal strength, while the second equalizer uses timing error detection to dynamically adjust tap coefficients based on clock signal timing deviations. This dynamic adaptation allows the system to automatically optimize performance for different transmission line characteristics without manual intervention
Data Source
AI summary
A semiconductor integrated circuit according to an embodiment includes an A/D converter, first and second equalizer circuits, and first and second controllers. The first equalizer circuit includes a first tap. The first and second equalizer circuits receive a signal based on a digital signal, and output first and second signals, respectively. The first controller adjusts a phase of a clock signal based on the first signal. The second controller an operation of adjusting a control parameter including a tap coefficient. In the operation, the second controller adjusts a tap coefficient of each of taps of the second equalizer circuit, and adjusts a tap coefficient of the first tap based on an adjustment result of each tap coefficient of the second equalizer circuit.