Receiver Equalizer Circuit Digital Down-Conversion Filtering
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Solution Overview
Problem
Existing receiver and transmitter equalizer circuits require high computational power due to the need for high sample rate processing, leading to resource inefficiency and increased power consumption.
Innovation Solution
The proposed solution involves placing the filter circuit downstream of the digital down-converters in the receiver equalizer circuit and upstream of the digital up-converters in the transmitter equalizer circuit, allowing the filter to operate at a reduced sample rate determined by decimation or interpolation factors, respectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If equalization is performed at high sample rate of ADC/DAC, then signal processing accuracy is improved, but computational power requirement and power consumption increase
Solution Approach 1:
The patent applies preliminary action by performing digital down-conversion before the equalization filtering operation. The digital down-converters (DDC) convert the high-sample-rate digitized signals to lower sample rate signals prior to filtering, so that the subsequent equalization filter operates at reduced computational complexity while still achieving the desired signal processing accuracy
Solution Approach 2:
The patent implements dynamics by making the processing rate adaptive to the actual signal bandwidth requirements. Instead of uniformly processing all signals at the maximum ADC/DAC sample rate, the system dynamically adjusts the processing rate to match the actual bandwidth needed, thereby reducing unnecessary computational operations and power consumption
2Reliability
If four real-valued filters and additional RF filter are provided for two parallel channels, then signal equalization is achieved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent applies merging by combining multiple separate filter operations into a single complex-valued filter per channel. Instead of requiring four separate real-valued filters for two parallel channels plus additional RF filters, the invention uses one complex filter per channel that processes both in-phase and quadrature components simultaneously, thereby reducing the total number of filter components while maintaining equalization quality
Solution Approach 2:
The patent implements universality by designing the complex-valued filter to perform multiple functions simultaneously. The complex filter handles both magnitude and phase correction, and processes both I and Q channel signals through a unified filtering structure, eliminating the need for separate real-valued filters and RF filters that would otherwise be required
Data Source
AI summary
A receiver equalizer circuit is described. The equalizer circuit includes a signal input, a first signal processing channel, a second signal processing channel, and a filter circuit. The first signal processing channel includes a first analog-to-digital converter and a first digital down-converter provided downstream of the first analog-to-digital converter. The second signal processing channel includes a second analog-to-digital converter and a second digital down-converter provided downstream of the second analog-to-digital converter. The filter circuit is connected to the signal processing channels downstream of the digital down-converters. Further, a transmitter equalizer circuit and an electronic device are described.