On-Die Receiver Eye-Opening Instrumentation Circuit
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Solution Overview
Problem
High-speed data links face challenges in accurately obtaining bit error data for eye-opening diagrams, as conventional methods lack efficient on-die instrumentation to effectively slice input data signals and recover valid error signals, especially at high data rates.
Innovation Solution
The implementation of a method using first and second sense amplifiers to generate speculative-high and speculative-low error signals, which are deserialized to produce error data, with a voltage and clock multiplexer system controlling reference voltages and clock signals to slice input data signals, allowing for the determination of invalid bits using clock-data recovery and decision feedback equalizer circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional off-chip probing methods are used to obtain receiver waveforms, then visibility to receive side data is limited, but on-die instrumentation adds circuit complexity and parasitic capacitance
Solution Approach 1:
The patent embeds instrumentation circuits (sense amplifiers, multiplexers, latches) directly within the receiver chip, nesting measurement functionality inside the existing receiver structure. This allows obtaining eye-opening diagrams and bit error data without external probing equipment, resolving the contradiction between measurement visibility and device complexity.
Solution Approach 2:
The receiver performs self-diagnosis by using its own internal resources (sense amplifiers, multiplexers, latches) to capture and analyze its received signals. The instrumentation circuitry monitors and measures the receiver's own performance, eliminating the need for external probing and reducing the contradiction between measurement capability and added complexity.
2Measurement precision
If multiple sense amplifiers are used to generate speculative-high and speculative-low error signals, then measurement precision improves, but parasitic capacitance and noise increase
Solution Approach 1:
The patent divides the measurement function into two separate sense amplifiers (first and second sense amplifiers) that independently generate speculative-high and speculative-low error signals. Each amplifier handles a specific portion of the measurement task, allowing precise bit error detection while managing parasitic capacitance by distributing the load across multiple specialized components rather than using a single complex amplifier.
Solution Approach 2:
The patent introduces multiplexers as intermediary components that selectively connect the output of sense amplifiers to latches based on control signals. These multiplexers act as mediators that manage the signals from multiple sense amplifiers, reducing direct interference and parasitic capacitance between amplifiers while maintaining measurement precision through controlled signal routing.
3Adaptability or versatility
If on-die instrumentation circuitry is added to generate eye-opening diagrams, then receiver configuration capability improves, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent designs the instrumentation circuitry (sense amplifiers, multiplexers, latches) to serve multiple functions: generating speculative-high and speculative-low error signals, capturing bit error data, and creating eye-opening diagrams. This multi-functionality allows the same circuit components to support various receiver configuration tasks, improving adaptability without proportionally increasing manufacturing complexity.
Solution Approach 2:
The patent combines the instrumentation functions (error signal generation, signal multiplexing, data latching) into an integrated on-die circuit block that works together as a unified system. By merging these functions into a cohesive instrumentation module rather than separate discrete components, the patent reduces overall device complexity and eases manufacturing while maintaining comprehensive receiver configuration capability.
Data Source
AI summary
One embodiment relates to a method performed by on-die instrumentation. Speculative-high and speculative-low error signals are generated using first and second sense amplifiers. The speculative-high and speculative-low error signals are deserialized to generate speculative-high and speculative-low error data. A subset of bits in the speculation-high and speculation-low error data are determined to be invalid based on prior bits in recovered data obtained using a clock-data recovery and decision feedback equalizer circuit. Another embodiment relates to an integrated circuit with on-die instrumentation for obtaining bit error data for an eye-opening diagram. The integrated circuit includes a voltage multiplexer, a clock multiplexer and first and second sense amplifiers. Other embodiments, aspects and features are also disclosed.