Receiver FFE Architecture With Gated Taps for Invalid Sample Periods
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Solution Overview
Problem
Implementing feed-forward equalization (FFE) circuits in receivers is challenging due to the need for back-channel communication and limited flexibility in peaking amplifiers, which affects signal quality and noise vulnerability.
Innovation Solution
The use of sample-and-hold circuitry with multiphase clocks to generate time-delayed versions of input signals and a current-integrating summer circuit with transconductance amplifier circuits, along with gating control signals, to enable efficient FFE implementation in receivers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If FFE is implemented in the transmitter, then implementation is easier and power/area costs are lower, but automatic adaptation requires back-channel communication and the received signal is smaller and more vulnerable to noise
Solution Approach 1:
The patent inverts the conventional approach by implementing FFE in the receiver rather than the transmitter. This allows automatic adaptation using LMS algorithms without requiring back-channel communication, as the equalizer coefficients are updated based on local error signals at the receiver side.
Solution Approach 2:
The patent implements feedback mechanisms at the receiver side, using the received signal to continuously adapt and update the FFE coefficients through LMS algorithms. This feedback loop enables automatic optimization of equalization performance without requiring communication back to the transmitter.
2Ease of manufacture
If peaking amplifiers are used in the receiver, then FFE implementation is simplified, but flexibility in pole and zero placement is limited and compatibility with adaptation algorithms is reduced
Solution Approach 1:
The patent employs dynamic and configurable circuit elements including variable gain amplifiers, adjustable delay elements, and programmable coefficients that allow the FFE to adapt its characteristics. This dynamic structure enables flexible pole and zero placement while maintaining compatibility with standard adaptation algorithms like LMS.
Solution Approach 2:
The patent utilizes adjustable parameters including variable tap coefficients, configurable delay values, and可调增益 settings that allow the equalizer to be precisely matched to different channel characteristics. These parameter changes enable both flexibility in implementation and compatibility with adaptation algorithms.
3Ease of operation
If conventional sample-and-hold circuitry is used, then time-delayed signals are generated, but tap extension beyond (n-1) limit is not possible
Solution Approach 1:
The patent merges multiple sample-and-hold circuits with overlapping integration periods to create an extended tap structure. By combining the outputs of multiple S/H circuits and using current-integrating summers, the system achieves tap extension beyond the conventional (n-1) limit, enabling the use of both pre-cursors and post-cursors.
Solution Approach 2:
The patent uses preliminary sampling and holding of the input signal at multiple phase offsets to prepare time-delayed versions of the signal before the integration period. This preliminary action enables the generation of extended taps including pre-cursors that occur before the main signal transition.
Data Source
AI summary
Circuits and methods are provided for efficient feed-forward equalization when sample-and-hold circuitry is employed to generate n time-delayed versions of an input data signal to be equalized. To equalize the input data signal, m data signals are input to m feed-forward equalization (FFE) taps of a current-integrating summer circuit, wherein each of the m data signals corresponds to one of the n time-delayed versions of the input data signal. A capacitance is precharged to a precharge level during a reset period of the current-integrating summer circuit. An output current is generated by each of the m FFE taps during an integration period of the current-integrating summer circuit, wherein the output currents from the m FFE taps collectively charge or discharge the capacitance during the integration period. A gating control signal is applied to an FFE tap during the integration period to disable the FFE tap during a portion of the integration period in which the data signal input to the FFE tap is invalid.