Receiver Circuit FIFO Buffering for High-Rate Code Block Decoding
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Solution Overview
Problem
Conventional receiver circuits face bottlenecks in data processing at high data rates, particularly in 5G systems like 3GPP new radio (NR), due to high load on the memory bus, making it challenging to achieve efficient data handling and processing.
Innovation Solution
A receiver circuit design that includes a decoder, on-chip FIFO memory, and a controller to manage data processing at the transport block level, allowing for efficient decoding and deciphering of code blocks without requiring large on-chip memory, and enabling re-transmissions through HARQ processes, with the option of using off-chip buffer memory to keep on-chip memory small and cost-efficient.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a common memory is used for data storage and processing in high data rate receiver circuits, then data processing capability is improved, but memory bus load becomes excessive and creates a bottleneck
Solution Approach 1:
The patent divides the memory system into two segments: a small on-chip FIFO memory for immediate data buffering and an off-chip buffer memory for storing incorrectly decoded code blocks. This segmentation allows the receiver to process high data rates without overwhelming the on-chip memory bus, as only essential data needs to be rapidly accessed on-chip while less time-critical data can be stored off-chip.
2Quantity of substance
If on-chip memory size is increased to handle high data rates, then data buffering capability is improved, but device cost and complexity increase
Solution Approach 1:
The patent extracts the buffer memory function from the on-chip memory and places it off-chip. The on-chip FIFO memory is reduced to only the size needed for immediate processing, while the larger buffer capacity is provided by off-chip memory. This extraction reduces on-chip complexity and cost while maintaining the necessary buffering capability for high data rate operation.
3Device complexity
If sequential processing of code blocks is used, then processing simplicity is maintained, but latency increases when re-transmissions are required
Solution Approach 1:
The patent implements preliminary action by storing incorrectly decoded code blocks in the off-chip buffer memory immediately when they occur, rather than waiting for re-transmission. When re-transmitted code blocks arrive, the system can quickly retrieve and process them without significant latency, as the buffer is already prepared. This maintains processing simplicity while reducing time loss compared to pure sequential processing.
Data Source
AI summary
The application relates to methods and devices for use in a receiver circuit (200) configured to receive data in transport blocks where each transport block comprises a set of individually decodable code blocks is provided. The receiver circuit comprises a decoder (102) for decoding the received data and at least one on-chip FIFO memory (210). The receiver circuit also comprises a Layer 2 decipher unit (104), and a buffer memory (106). In the receiver circuit, a controller (220) is provided. The decoder is configured to store a correctly decoded code block in the at least one on-chip FIFO memory, and when a code block of a transport block is incorrectly decoded, store any subsequent correctly decoded code block of the same transport block in the buffer memory. Hereby an efficient receiver circuit that can be implemented using a small on-chip memory is provided.