Baseband Receiver Filter-ADC Integration for Low-Jitter Wideband Design
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Solution Overview
Problem
Current radio receiver designs face challenges in minimizing silicon area and power consumption while maintaining filtering performance, especially with increasing bandwidth requirements, and struggle with clock jitter and noise shaping at wider bandwidths.
Innovation Solution
The design incorporates a shared circuitry approach between the analog baseband filter stage and the analog-to-digital converter, utilizing feedback paths to relax ADC specifications, reduce power consumption, and enhance noise shaping, allowing for lower oversampling ratios and improved frequency selectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If filtering and ADC are merged in present solutions, then power consumption and silicon area are reduced, but clock jitter specifications become very low thus increasing power consumption and silicon area for clock generation and distribution
Solution Approach 1:
The patent extracts the feedback DAC from the merged filtering-ADC structure and replaces it with a digital feedback path. This separation removes the clock jitter sensitivity issue while maintaining the area and power benefits of the merged structure. The digital feedback path eliminates the need for high-precision clocking in the feedback loop.
Solution Approach 2:
The patent introduces a digital domain as an intermediary between the analog filter and the ADC feedback. By converting the feedback signal to digital and processing it there, the system avoids the clock jitter problems of direct analog feedback while maintaining signal integrity.
2Speed
If bandwidth is increased in 4.5G and 5G, then data rate is improved, but receiver silicon area and current consumption should be minimized
Solution Approach 1:
The patent merges the baseband filter and ADC into a single integrated structure, reducing the total silicon area required. The shared components and overlapping signal paths eliminate redundant circuitry while maintaining both wide bandwidth capability and area efficiency.
Solution Approach 2:
The merged filtering-ADC structure performs multiple functions simultaneously: baseband filtering, signal conversion, and feedback processing. This multi-functionality reduces the overall component count and silicon area while supporting wide bandwidth requirements for 4.5G and 5G.
3Speed
If bandwidth is increased, then data rate is improved, but power consumption increases
Solution Approach 1:
The integrated filtering-ADC structure shares common components and signal paths, reducing redundant power consumption. The merged design eliminates separate power supplies and control logic for independent filter and ADC operations, lowering overall current consumption while maintaining wide bandwidth performance.
4Manufacturing precision
If feedback DAC is used in present solutions, then filtering is achieved, but clock jitter requirements increase power consumption and silicon area
Solution Approach 1:
The patent removes the feedback DAC from the system and replaces it with a digital feedback path. This extraction eliminates the clock jitter sensitivity and associated power consumption of the DAC while maintaining filtering performance through the digital domain processing.
Solution Approach 2:
The patent replaces the analog feedback DAC mechanism with a digital processing approach. By moving the feedback function to the digital domain, the system eliminates the need for high-precision analog-to-digital conversion in the feedback loop, reducing power consumption and clock jitter requirements.
Data Source
AI summary
A receiver is described, the receiver comprising an ABB filter stage, an ADC stage. The ABB filter stage comprises an ABB filter stage input configured to receive an analog baseband, BB, signal and an ABB filter stage output configured to provide a filtered analog BB signal. The ADC stage comprises an ADC stage input configured to receive the filtered analog BB signal and an ADC stage output configured to provide a digital BB signal. The ADC stage comprises an ADC comprising an ADC input configured to receive the filtered analog BB signal or a signal derived therefrom as an ADC input signal, and wherein the ADC is configured to perform an analog-to-digital, A/D, conversion of the ADC input signal to derive the digital BB signal.