Baseband Receiver Filter-ADC Sharing for Low-Jitter Wideband Conversion
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Solution Overview
Problem
Current telecommunications receiver designs face challenges in minimizing silicon area and power consumption while maintaining filtering performance, especially with increasing bandwidth requirements, and struggle with clock jitter and noise shaping at wider bandwidths.
Innovation Solution
The proposed receiver design shares circuitry between the analog baseband filter stage and the ADC, eliminating the need for a first feedback DAC, and uses a second feedback path with a D/A converter and delay element to achieve low power consumption and improved frequency selectivity, allowing for lower oversampling ratios and reduced noise transfer function notch frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If filtering and continuous-time delta-sigma ADCs are merged to reduce area and power, then silicon area and power consumption are reduced, but clock jitter specifications become very low increasing power consumption and silicon area for clock generation
Solution Approach 1:
The patent divides the feedback signal into two separate paths: an analog feedback path that feeds the ADC input signal to the ABB filter stage, and a digital feedback path that feeds the digital BB signal. This segmentation eliminates the need for a first feedback DAC in the analog path, thereby relaxing clock jitter requirements and reducing power consumption for clock generation while maintaining the merged filtering-ADC architecture for area efficiency.
2Speed
If the bandwidth is increased from hundreds of kilohertz to tens or hundreds of megahertz, then the radio channel capacity is improved, but the flexibility requirements for baseband filtering and power consumption increase
Solution Approach 1:
The patent merges the ABB filter stage with the ADC stage by sharing circuitry between them. The ABB filter stage processes the analog baseband signal and feeds it to the ADC, while feedback paths provide signal correction. This merging reduces the overall power consumption compared to having separate filtering and ADC stages, enabling the system to handle wide bandwidths (tens to hundreds of megahertz) efficiently.
3Manufacturing precision
If a first feedback DAC is used in the analog feedback path, then filtering performance is maintained, but clock jitter requirements become very low increasing power consumption
Solution Approach 1:
The patent extracts the DAC function from the analog feedback path and relocates it to the digital feedback path. The analog feedback path directly connects the ADC input signal to the ABB filter stage without a DAC, eliminating the clock jitter issue. The DAC functionality is preserved in the digital feedback path where it operates on digital signals, maintaining filtering performance while reducing power consumption.
4Speed
If the oversampling ratio is reduced to increase bandwidth coverage, then the filter bandwidth is improved, but noise shaping effectiveness is reduced
Solution Approach 1:
The patent implements dual feedback paths to maintain noise shaping effectiveness at low oversampling ratios. The analog feedback path provides continuous correction of the ADC input signal, while the digital feedback path corrects the digital BB signal. This feedback mechanism compensates for reduced noise shaping that would normally occur at low OSR, allowing wide bandwidth operation while maintaining signal quality.
Data Source
AI summary
A receiver is described, the receiver comprising an ABB filter stage, an ADC stage. The ABB filter stage comprises an ABB filter stage input configured to receive an analog baseband, BB, signal and an ABB filter stage output configured to provide a filtered analog BB signal. The ADC stage comprises an ADC stage input configured to receive the filtered analog BB signal and an ADC stage output configured to provide a digital BB signal. The ADC stage comprises an ADC comprising an ADC input configured to receive the filtered analog BB signal or a signal derived therefrom as an ADC input signal, and wherein the ADC is configured to perform an analog-to-digital, A/D, conversion of the ADC input signal to derive the digital BB signal.