Receiver Front End Architecture for Intra-Band Carrier Aggregation

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Solution Overview

Problem

Conventional wireless device front ends face challenges in efficiently amplifying and routing radio frequency signals across a wide frequency range due to significant circuit area requirements and difficulty in compensating for gain and routing losses, especially in carrier aggregation systems.

Innovation Solution

A novel receiver front end architecture with a Signal Amplification and Routing Circuit (SARC) that utilizes fewer amplifier degeneration inductors, featuring configurable cascode amplifiers and control signals to dynamically route RF signals across multiple band groups, reducing noise and circuit area while maintaining linearity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If multiple amplifiers with degeneration inductors are used to amplify multiple carrier signals, then amplification capability is improved, but circuit area increases significantly

Engineering Contradiction:
Improveamplification capabilityVSAvoidcircuit area
Core Design Contradiction:
PowerVSArea of stationary object

Solution Approach 1:

The patent combines multiple amplifier functions into a single amplifier by using configurable routing circuits that can direct different carrier signals to different output paths. This merging approach eliminates the need for multiple separate amplifiers with their associated degeneration inductors, significantly reducing circuit area while maintaining the capability to amplify multiple carrier signals simultaneously

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The single amplifier is designed to serve multiple functions by amplifying different carrier signals routed to different outputs through the configurable routing circuits. The amplifier acts as a universal amplification resource that can be dynamically allocated to different carrier aggregation configurations, replacing multiple dedicated amplifiers

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Area of stationary object

If amplifiers are spread across multiple chips, then circuit area is reduced, but difficulty in compensating for gain and routing losses increases

Engineering Contradiction:
Improvecircuit areaVSAvoidcompensation complexity
Core Design Contradiction:
Area of stationary objectVSDevice complexity

Solution Approach 1:

The patent integrates the amplifier and routing compensation functions into a unified architecture where the routing circuits are configured to compensate for gains and losses occurring in the signal path. By keeping the amplification and routing functions closely integrated rather than distributed across multiple chips, the system simplifies the compensation of gain and routing losses while still achieving area reduction through the shared amplifier approach

Inventive Principle:
Principle #5Merging (Combining)

3Ease of manufacture

If conventional front end architecture is used, then implementation is simple, but linearity and gain compensation become difficult

Engineering Contradiction:
Improveimplementation simplicityVSAvoidlinearity and gain compensation
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent introduces dynamic configurability to the front end architecture through control circuits that can adjust the routing of carrier signals based on operating conditions. This dynamic approach allows the system to optimize linearity and gain compensation for different carrier aggregation configurations while maintaining a relatively simple base architecture, bridging the gap between simplicity and performance

Inventive Principle:
Principle #15Dynamics

Data Source

PatentEP3219016B1Receiver front end architecture for intra band carrier aggregation
Publication Date: 2019.07.10 QUALCOMM INC
  • EP3219016B1 patent drawingFigure 1~2
  • EP3219016B1 patent drawingFigure 3
  • EP3219016B1 patent drawingFigure 4

AI summary

A receiver front end architecture for intra band carrier aggregation is disclosed. In an exemplary embodiment, an apparatus includes a first transistor having a gate terminal to receive an input signal, drain terminal to output an amplified signal, and a source terminal connected to a signal ground by a source degeneration inductor. The apparatus also includes a second transistor having a source terminal connected to the drain terminal of the first transistor and a drain terminal connected to a first load. The apparatus also includes a third transistor having a gate terminal connected to the drain terminal of the first transistor, a drain terminal connected to a second load and a source terminal connected to a signal ground.