Receiver Hysteresis Circuit With 2VDD Biasing for Signal Reflection
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Solution Overview
Problem
The increasing bandwidth requirements in 5G mobile phones lead to signal glitches due to signal reflection, which compromises signal integrity in communication between application processors and peripheral devices on printed circuit boards.
Innovation Solution
A hysteresis circuit with an overdrive voltage (2VDD) and a protection circuit using multiple bias voltages is implemented to enhance signal integrity, featuring an inverter and latch with positive feedback control, expanding the hysteresis window and improving signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data clock frequency is increased to meet bandwidth requirements, then communication speed between AP and peripheral devices is improved, but signal reflection and glitches occur compromising signal integrity
Solution Approach 1:
The patent converts the harmful signal reflection into a beneficial effect by using the reflected signal power to bias the protection circuit. The reflection that would normally cause glitches is instead utilized to provide the necessary bias voltages for the first and second sub-circuits, transforming a harmful phenomenon into a useful function that maintains signal integrity at high frequencies
Solution Approach 2:
The patent changes the voltage parameters by using an overdrive voltage (2VDD) which is twice the normal power supply voltage (VDD). This parameter change allows the hysteresis circuit to operate effectively at higher frequencies while maintaining signal integrity, as the increased voltage headroom compensates for the signal degradation caused by reflection
2Reliability
If hysteresis circuit with overdrive voltage (2VDD) is implemented, then signal integrity is enhanced by widening hysteresis window, but device complexity increases due to protection circuit with multiple bias voltages
Solution Approach 1:
The protection circuit is designed to perform multiple functions simultaneously: it provides bias voltages for the hysteresis circuit, handles signal conditioning, and protects against voltage excursions. By integrating these multiple functions into a single protection circuit block, the patent reduces overall device complexity compared to having separate circuits for each function
Solution Approach 2:
The protection circuit uses the reflected signal power to generate its own bias voltages, making the circuit self-sufficient. The first sub-circuit generates a bias voltage lower than VDD, and the second sub-circuit generates a bias voltage higher than VDD, without requiring external bias generation circuits, thereby simplifying the overall device structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly enhances signal integrity by widening the hysteresis window, ensuring reliable binary digit transmission and addressing signal reflection issues, thereby improving communication between application processors and peripheral devices.
Implementation Method 1
the latch is coupled to the inverter for positive feedback control
Implementation Method 2
Through the first sub-circuit of the protection circuit, the input is coupled to the inverter to control the pull-up path of the inverter. Through the second sub-circuit of the protection circuit, the input is coupled to the inverter to control the pull-down path of the inverter
Data Source
Figure 1
Figure 2A
Figure 2B
AI summary
A hysteresis circuit to be produced within a receiver of a chip is shown. The hysteresis circuit is powered by an overdrive voltage (2VDD), and has a protection circuit, an inverter, and a latch. The input of the hysteresis circuit is coupled to the inverter through the protection circuit, to be transformed into an output, and the latch is coupled to the inverter for positive feedback control. The protection circuit has a first sub-circuit (coupling the input to the inverter to control the pull-up path of the inverter) biased by a first bias voltage that is lower than VDD, and a second sub-circuit (coupling the input to the inverter to control the pull-down path of the inverter) biased by a second bias voltage that is greater than VDD.