Receiver IR Buffer Externalization for SoC Area Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing air interface communication rate in wireless channels leads to a rapid increase in the size of the IR buffer within the SoC, occupying over 20% of the SoC area and increasing costs, due to the need for incremental redundancy processing in HARQ mechanisms.
Innovation Solution
A receiver architecture with a system on chip connected to an external memory through a buffer bus, incorporating a logarithmic likelihood ratio subsystem, controller, rate matching module, and incremental redundancy reconstructing module, which demodulates, stores, and combines data blocks efficiently, reducing the need for internal buffering and optimizing memory usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the IR buffer size is increased to support higher air interface communication rates, then the data processing capability is improved, but the SoC area occupied increases by over 20% and cost increases
Solution Approach 1:
The patent extracts the IR buffer from the SoC internal memory and relocates it to external memory. The controller manages the IR buffer in external memory, which significantly reduces the SoC area occupied by the IR buffer while maintaining the data processing capability required for higher air interface communication rates
Solution Approach 2:
The patent transitions the IR buffer from a two-dimensional on-chip memory structure to a three-dimensional architecture utilizing off-chip external memory. This dimensional change allows the IR buffer to scale with communication rate requirements without proportionally increasing the SoC footprint
2Productivity
If the IR buffer size is increased to support higher air interface communication rates, then the data processing capability is improved, but the receiver cost increases
Solution Approach 1:
The patent extracts the IR buffer from the expensive on-chip memory resources and relocates it to external memory, which is more cost-effective for large capacity storage. This extraction reduces the high-cost on-chip memory requirements while maintaining the necessary data processing capability for high-rate communications
Solution Approach 2:
The patent utilizes external memory, which is a more economical storage solution compared to on-chip memory. Although external memory requires additional interface circuitry, the overall cost is reduced because external memory can provide the required large capacity at a lower cost per bit
3Area of stationary object
If LLR data is stored in external memory, then the SoC cost is reduced, but the data bandwidth requirement increases
Solution Approach 1:
The patent changes the data representation parameters by storing LLR data in a compact format in external memory. The controller manages data width and formatting to optimize the balance between external memory bandwidth requirements and SoC area reduction, allowing efficient use of the external buffer bus
Data Source
AI summary
The present invention discloses a receiver and a method for data processing. The receiver includes a system on chip and a memory, where the system on chip is connected to the memory through an external buffer bus; the system on chip includes an LLR subsystem, a controller, a rate matching module, an incremental redundancy IR reconstructing module, and a combiner, where the LLR subsystem is connected to the controller and the rate matching module respectively; the controller is connected to the IR reconstructing module, and the rate matching module and the IR reconstructing module are connected to the combiner respectively; and the controller stores LLR data currently corresponding to a data block demodulated by the LLR subsystem into a memory, and read LLR data historically corresponding to the data block and stored in the memory into the IR reconstructing module when the data block is a retransmitted data block.