Receiver Lane Synthesized Clock Source for BIST
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Solution Overview
Problem
Existing multilane receiver systems require dedicated clock sources for Built-In-Self-Test (BIST) operations, which consume significant SoC area and increase power consumption, as they need to generate high-frequency clock signals for testing functionality, whereas normal operation uses lower frequency reference clocks.
Innovation Solution
Implementing a system where at least one receiver lane acts as a synthesized clock source for other receiver lanes during BIST operations, using digital signals to manage the configuration and provide a high clock rate for accurate testing without dedicated clock sources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If dedicated clock sources are used for BIST operations, then accurate high-frequency clock signals are generated for testing, but SoC area and power consumption increase significantly
Solution Approach 1:
The receiver lane is designed to perform multiple functions: during normal operation it receives data streams, and during BIST operations it generates clock signals and transmits test patterns. This multi-functionality eliminates the need for dedicated clock sources while maintaining testing accuracy through the use of existing high-speed receiver components
Solution Approach 2:
The patent combines the clock generation function with the receiver lane functionality. The receiver lane's CDR circuitry and high-speed components are utilized to generate clock signals and transmit test patterns, merging previously separate functions into a single integrated unit that reduces SoC area
2Measurement precision
If dedicated clock sources are used for BIST operations, then high-frequency clock signals are generated for accurate testing, but power consumption increases
Solution Approach 1:
The receiver lane performs both data reception and clock generation functions, eliminating the need for separate dedicated clock sources. This reduces overall power consumption by utilizing the existing power-efficient high-speed components already present in the receiver lane for dual purposes
Solution Approach 2:
The receiver lane serves itself by generating its own clock signals and transmitting test patterns using its internal components. The CDR circuitry and high-speed serial interface are utilized to create the necessary clock signals without requiring external dedicated clock generation hardware, thereby reducing power consumption
3Use of energy by stationary object
If receiver lanes use low-frequency reference clocks for normal operation, then power consumption is reduced, but high-frequency clock signals are needed for BIST operations
Solution Approach 1:
The receiver lane dynamically switches between operating modes: during normal operation it uses low-frequency reference clocks for power-efficient data reception, while during BIST operations it activates high-frequency clock generation using its CDR circuitry. This dynamic mode switching allows the system to meet different frequency requirements without continuously consuming high power
Solution Approach 2:
The system changes the clock frequency parameter based on operational mode. During normal operation, low-frequency reference clocks are used to minimize power consumption. During BIST operations, the same receiver lane generates high-frequency clock signals by utilizing its CDR circuitry to synthesize appropriate clock rates, thereby adapting the frequency parameter to match operational requirements
Data Source
AI summary
Built-in-self-test (BIST operations are performed by receiver lanes of a multilane receiver system, wherein at least one receiver lane is configured as a synthesized clock source for other receiver lanes configured to perform BIST operations. The at least one receiver lane configured as the synthesized clock source may generate a clock signal and provide the clock signal to the other receiver lanes performing the BIST operations. In some examples, digital control signals may be used for coordinating the enablement of the at least one receiver lane to function as the synthesized clock source and for coordinating the enablement of the other receiver lanes to perform BIST operations.