Receiver Lane Shifting for High-Speed Frame Boundary Alignment
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Solution Overview
Problem
Conventional methods for frame alignment in high-speed communications, such as using de-skewing FIFO components, reduce data transfer rates, decrease data bandwidth, and cause increased latency due to repeated synchronization processes.
Innovation Solution
A method utilizing shifting logic in the receiver to synchronize each data lane with respect to the frame boundary, employing a non-aliasing repeated pattern and count pattern to align all data lanes with a common frame boundary, reducing the need for repeated framing symbols.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If de-skewing FIFO components are used for frame alignment, then data synchronization is achieved, but data transfer rate is reduced
Solution Approach 1:
The patent extracts and removes the de-skewing FIFO component from the data path. By eliminating this synchronization component, the system achieves frame alignment through an alternative method (using frame alignment symbols and detection logic) that does not introduce the bandwidth limitations and latency associated with FIFO-based de-skewing, thereby maintaining high data transfer rates while still achieving synchronization.
Solution Approach 2:
The patent implements preliminary frame alignment by inserting known frame alignment symbols at the beginning of data transmissions and using detection logic to identify these symbols before actual data processing begins. This preliminary synchronization action establishes frame boundaries in advance, allowing subsequent data transfer to proceed without the need for continuous de-skewing FIFO operations, thus maintaining high transfer rates.
2Reliability
If de-skewing FIFO components are used for frame alignment, then data synchronization is achieved, but data bandwidth is decreased
Solution Approach 1:
The patent removes the de-skewing FIFO component that was constraining data bandwidth. By replacing FIFO-based synchronization with frame alignment symbol detection, the system eliminates the bandwidth reduction effect caused by FIFO buffering and de-skewing operations, thereby maximizing available data bandwidth while maintaining synchronization reliability.
Solution Approach 2:
By performing frame alignment detection using predetermined symbols before data transfer begins, the system establishes synchronization once rather than continuously buffering data through FIFO components. This preliminary action eliminates the ongoing bandwidth consumption associated with FIFO operations, preserving maximum data bandwidth for actual payload transmission.
3Reliability
If synchronization process is repeated each time data transmission is stopped and restarted, then frame alignment is maintained, but latency is increased
Solution Approach 1:
The patent implements a dynamic frame alignment approach where the system detects whether data transmission is continuous or has been interrupted. When transmission is continuous, the system maintains existing frame alignment without re-synchronization. When transmission stops and restarts, the system dynamically inserts frame alignment symbols and performs detection. This conditional, adaptive approach minimizes unnecessary re-synchronization operations and their associated latency while maintaining frame alignment reliability.
Solution Approach 2:
Instead of performing full re-synchronization every time transmission stops and restarts, the patent applies partial action by only performing frame alignment detection when actually needed (i.e., when interruption is detected). This selective approach avoids the excessive latency of repeated full synchronization processes while maintaining sufficient frame alignment through the use of frame alignment symbols only when necessary.
Data Source
AI summary
A system includes a transmitter device and a receive device coupled to a link having data lanes. The receiver device includes training logic. Each of the plurality of data lanes is to receive, from the transmitter device, an incoming data stream having the same pattern repeated over the plurality of clock cycles, and the training logic is to shift the incoming data stream one unit interval (UI) at a time until a shifted data pattern matches an expected data pattern on each data lane. Each of the plurality of data lanes is to receive, from the transmitter device, a count value at every clock cycle, and the training logic is to shift one or more burst lengths (BLs) until each data lane receives a same count value, thereby synchronizing the data lanes to a common frame boundary.