Receiver Compensation Filter for Sampling Frequency and Phase Offset
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Solution Overview
Problem
In ultra-high-speed wireless communication systems, frequency offsets between the transmitter and receiver lead to inaccurate data restoration due to shifting symbol timing, and existing compensation methods are inefficient, particularly in high-speed scenarios where synchronization is challenging and require large circuit configurations.
Innovation Solution
A digital circuit performs on-the-fly compensation for sampling frequency and phase offsets using a tapped filter and adaptive algorithm, without matching the receiver clock to the transmitter clock, and with minimal oversampling, allowing for compact circuit design and continuous data restoration without relying on training sequences or pilot words.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If digital resampling circuit is used to compensate frequency offset, then data restoration accuracy is improved, but circuit size and processing time increase
Solution Approach 1:
The patent extracts only the essential function of frequency offset compensation from the complex digital resampling circuit. By using a simplified digital circuit that performs only the necessary frequency and phase offset compensation without full resampling functionality, the circuit size is dramatically reduced while maintaining the ability to restore data accurately.
Solution Approach 2:
The patent performs frequency and phase offset compensation immediately after synchronization is achieved, before the sampling position shifts significantly. This preliminary action prevents the need for complex subsequent resampling operations, reducing both circuit size and processing time while maintaining data restoration accuracy.
2Reliability
If analog PLL is used for symbol time restoration, then frequency synchronization is achieved, but high-speed synchronization is not possible
Solution Approach 1:
The patent replaces the analog PLL (a continuous, slow-adjustment system) with a digital circuit that can rapidly calculate and apply frequency and phase offset corrections. This substitution enables high-speed synchronization while maintaining reliable frequency synchronization, as the digital circuit can process and adjust parameters much faster than analog components.
3Measurement precision
If oversampling is performed multiple times, then sampling accuracy is improved, but circuit complexity and power consumption increase
Solution Approach 1:
The patent applies just enough oversampling to achieve the necessary sampling accuracy for ultra-high-speed communication, rather than performing excessive oversampling. By combining moderate oversampling with rapid digital frequency and phase offset compensation, the system achieves high sampling accuracy with minimal power consumption, as the digital compensation corrects any remaining errors without requiring multiple oversampling passes.
Data Source
AI summary
Received data oversampled twice is polyphased by the receiver, feedback is applied using an adaptive algorithm, and the filter coefficients (tap coefficient sequence) of a compensation filter are simultaneously shifted when the data shifts. The sampling frequency and the phase offset can be compensated for on the fly using a filter combining a tapped filter whose initial value is a correlation value obtained from the preamble and header of a received signal, and a wavefront aligner. In this configuration, a resampling filter circuit, an equalization filter circuit and a decimation filter circuit are realized in a single compensation filter circuit, which is much smaller than the prior art circuits in terms of size.