Receiver Offset Compensation Circuit for Differential Signal Mismatch

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing receivers face challenges in detecting and compensating for offset voltages in differential signals due to mismatches or asymmetric aging of paired elements, which affect the Ratio of Level separation Mismatch (RLM) and eye diagram margin.

Innovation Solution

A receiver is designed with an offset voltage detection circuit that includes a differential signal generator, a boundary detector, a comparator, a voting unit, and digital-analog converters (DACs), which detect and compensate for offset voltages without using separate voltage or current sources by adjusting reference and compensation signals based on offset detection signals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If separate voltage or current sources are used for offset voltage detection, then detection accuracy is improved, but device complexity and power consumption increase

Engineering Contradiction:
Improveoffset voltage detection accuracyVSAvoidcircuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent merges the offset voltage detection function with the existing differential signal processing circuitry. The detection circuit reuses the differential signal generator, boundary detector, and comparator that already exist in the receiver, eliminating the need for separate voltage or current sources. This integration maintains detection accuracy while reducing device complexity and power consumption.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The comparator and boundary detector are designed to serve multiple functions: they detect both the offset voltage of the differential signal and the boundary levels of the signal. By making these components multi-functional, the patent avoids adding separate detection circuits, thereby reducing overall device complexity while maintaining the required measurement precision.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If offset compensation is implemented, then noise margin and signal quality are improved, but device complexity increases

Engineering Contradiction:
Improvenoise marginVSAvoidcircuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements a feedback mechanism where the detected offset voltage is fed back to the differential signal generator through the offset compensator. The compensator adjusts the compensation signals based on the detected offset, creating a closed-loop system that automatically maintains signal quality and noise margin without requiring complex external control circuits.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The offset compensation system is self-regulating. The same comparator that detects the offset also generates the error signal that drives the compensation process. The boundary detector automatically adapts to signal levels, and the entire compensation mechanism operates autonomously without external intervention, reducing the need for additional control complexity.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS11817861B2Receiver including offset compensation circuit
Publication Date: 2023.11.14 SAMSUNG ELECTRONICS CO LTD
  • US11817861B2 patent drawing
  • US11817861B2 patent drawing
  • US11817861B2 patent drawing

AI summary

A receiver includes a differential signal generator receiving a single-ended signal, and generating differential signals having a positive signal and a negative signal based on the single-ended signal, a reference signal, and a pair of compensation signals, a pair of charging circuits charging first and second nodes to a power level in a logic low period of a clock signal, a pair of discharging circuits discharging the first and second nodes according to a level of the positive signal and a level of the negative signal, respectively, in a logic high period of the clock signal, a comparator comparing signal levels of the first and second nodes and outputting an offset detection signal of the differential signals, and an offset compensator outputting the reference signal and the pair of compensation signals, each adjusted based on the offset detection signal, to the differential signal generator.