Receiver Packet Format for Variable Address Length Processing
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Solution Overview
Problem
Existing communication protocols face inefficiencies due to complex multiplexing logic required for varying address lengths, leading to changes in payload and error checking bit positions, which complicates data packet processing in receiver circuits.
Innovation Solution
The proposed solution involves modifying data packet formats where additional bits for longer address lengths are appended at the end, maintaining consistent bit positions for core fields like preamble and data, and using shift registers with multiplexers to efficiently load and process serial data signals based on selected packet formats.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If variable address lengths are supported in communication protocols, then adaptability is improved, but device complexity increases due to complex multiplexing logic required for varying address lengths and changing payload/error checking bit positions
Solution Approach 1:
The data packet is segmented into fixed-position core fields (preamble, data, error checking) and variable address fields. The address field is further divided into most significant bits at fixed positions and least significant bits that can be appended. This segmentation allows the receiver to process core fields with simple fixed logic while accommodating variable address lengths through controlled appending at the end of the packet.
Solution Approach 2:
The patent introduces a dimensional approach by separating address bits into two groups: most significant bits positioned in the upper addresses (fixed position) and least significant bits in the lower addresses (variable position). This dimensional separation transforms the problem from handling variable-length packets to handling variable-position bits within a fixed structure, simplifying the multiplexing logic.
2Productivity
If consistent bit positions are maintained for core fields, then processing efficiency is improved, but adaptability worsens due to limitations in handling variable address sizes
Solution Approach 1:
The address field is segmented into most significant bits (MSBs) and least significant bits (LSBs). MSBs are placed at fixed upper address positions to maintain consistency for core field positioning, while LSBs are appended at lower positions to provide variable address size capability. This segmentation resolves the contradiction by allowing both fixed-position processing and variable-length accommodation.
Solution Approach 2:
The patent establishes a predetermined packet structure where core fields (preamble, data, error checking) are assigned fixed bit positions in advance. This preliminary structuring allows the receiver to efficiently process these fields without complex dynamic positioning logic, while still accommodating variable address sizes through the appended LSB approach.
Data Source
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AI summary
The disclosure relates to a system comprising a processing circuit and a circuit (230a) configured to provide at output a given number NA2 of bits of configuration information (A_CFG) to be used by said processing circuit. The circuit (230a) comprises a non-volatile programmable memory (2300) providing at output a first group (A_CFG1) of NA2 bits. The circuit (230a) may comprise also NA2 terminals for receiving a second group (A_CFG2) of N42 bits and NA2 logic gates (2304). In this case, a first input terminal of each logic gate (2304) may be connected to a respective bit of the output of the non-volatile programmable memory (2300) providing at output the first group (A_CFG1) of NA2 bits, and a second input terminal of each logic gate (2304) may be connected to a respective terminal of the NA2 terminals for receiving the second group of NA2 bits. In addition, or alternatively, the circuit (230a) may comprises a further memory (2306) providing at output a third group (A_CFG3) of NA2 bits and NA2 logic gates (2308). In this case, a first input terminal of each logic gate (2308) may be connected to a respective bit of the output of the non-volatile programmable memory (2300) providing at output the first group (A_CFG1) of NA2 bits, and a second input terminal of each logic gate (2308) may be connected to a respective bit of the output of the further memory (2306) providing at output the third group (A_CFG3) of NA2 bits.