Serial Data Receiver Phase Alignment for Low Bit Error Sampling
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Solution Overview
Problem
High-speed communication channels in integrated circuits face increased bit error rates due to phase differences between data and error clock signals, which can be exacerbated by manufacturing inconsistencies and noise, leading to reduced data transfer bandwidth and higher costs with multiple channels.
Innovation Solution
A receiver circuit with a phase compensation circuit that adjusts the phase difference between data and error clock signals by sampling a reference signal to generate data and error samples, allowing for alignment of these signals and reducing bit error rates through decision feedback equalization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the data rate on a communication channel is increased, then the bandwidth and productivity are improved, but the data window for valid data bits decreases and bit error rate increases
Solution Approach 1:
The patent implements decision feedback equalization where error samples are fed back to adjust receiver characteristics. The phase compensation circuit uses error samples to detect phase differences between data and error clock signals, then adjusts sampling timing to compensate for skew, thereby reducing bit error rates at high data rates
Solution Approach 2:
The patent dynamically adjusts sampling parameters including phase offset and timing based on detected error patterns. The receiver modifies sampling clock phase and timing parameters in response to measured signal conditions, optimizing the data window sampling point to maintain low bit error rates despite reduced window duration at higher data rates
2Measurement precision
If phase difference between data and error clock signals is not compensated, then device complexity is reduced, but measurement precision and reliability deteriorate due to increased bit error rate
Solution Approach 1:
The phase compensation circuit performs self-calibration by using its own error samples to detect phase differences and adjust its timing. The circuit automatically measures the phase skew between data and error clocks during operation and compensates without external intervention, maintaining sampling precision while avoiding complex external calibration equipment
Solution Approach 2:
The patent implements preliminary phase calibration during a training mode before normal data transmission. The receiver pre-adjusts sampling timing based on initial error sample analysis, establishing optimal sampling points before actual data reception begins, thereby ensuring measurement precision from the start of data transfer
3Productivity
If multiple communication channels are used to increase data rate, then productivity is improved, but costs and device complexity increase
Solution Approach 1:
The phase compensation circuit serves multiple functions: it compensates for phase skew in the current channel, calibrates timing for both data and error sampling, and provides adaptive equalization. This multi-functionality allows a single receiver circuit to handle high-rate transmission without requiring additional dedicated compensation circuits for each channel
Data Source
AI summary
An apparatus includes a receiver buffer, a phase compensation circuit, a data sampler circuit, and an error sampler circuit. The receiver buffer may generate an equalized signal on a signal node using an input signal received via a channel. The phase compensation circuit may, in response to an initiation of a training mode, replace the equalized signal on the signal node with a reference signal. The data sampler circuit may sample, using a data clock signal, the reference signal to generate a plurality of data samples. The error sampler circuit may sample, using an error clock signal, the reference signal to generate a plurality of errors samples. The phase compensation circuit may also adjust a phase difference between the data clock signal and the error clock signal using at least some of the plurality of data samples and at least some of the plurality of error samples.