Data Link Receiver Phase Calibration for Low-Power Die-to-Die I/O
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Solution Overview
Problem
High-performance computing applications require significant processing power and efficient data communication between circuits, which is hindered by high power consumption and latency in die-to-die communication within IC packages.
Innovation Solution
Implement phase calibration at data link transmitters and receivers to align clock phases, use clock-forwarded data link signaling to save power, and employ clock forwarding between deserializer and FIFO to achieve zero-cycle entry and exit, along with lane alignment and flow control optimization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high bandwidth data communication is implemented between dice, then processing power and data transfer capability are improved, but power consumption increases significantly
Solution Approach 1:
The patent performs phase calibration in advance before data transmission begins. The calibration process aligns the phases of parallel clocks at transmitter and receiver, and matches phases across multiple data lanes. This preliminary synchronization ensures that subsequent high-speed data communication can proceed efficiently without requiring continuous power-intensive recalibration, thus enabling high productivity while managing power consumption.
2Measurement precision
If phase calibration is performed to align clock phases, then data transmission accuracy is improved, but calibration time and complexity increase
Solution Approach 1:
The patent divides the calibration process into distinct segments: parallel clock phase alignment at the transmitter, serial clock phase matching at the receiver, and individual data lane phase calibration. Each segment is handled by dedicated circuitry (parallel clock phase alignment circuitry, serial clock phase alignment circuitry, lane alignment circuitry), which simplifies the overall complexity by breaking down the monolithic calibration task into manageable, specialized components.
Solution Approach 2:
The patent introduces intermediary calibration circuits that act as mediators between the parallel and serial clock domains. These intermediary circuits (phase calibration circuits, lane alignment circuits) facilitate the complex phase matching task by providing intermediate synchronization points, making the overall calibration process more manageable and precise.
3Loss of time
If clock forwarding is implemented between deserializer and FIFO, then latency is reduced to achieve zero-cycle entry and exit, but timing synchronization becomes more difficult
Solution Approach 1:
The patent performs comprehensive phase calibration before data transmission, ensuring that all clock phases (parallel clocks at transmitter, serial clocks at receiver, and data lane clocks) are预先 aligned. This preliminary synchronization eliminates the need for complex real-time timing adjustments during data flow, enabling the clock-forwarding technique to achieve zero-cycle latency without overwhelming timing synchronization complexity.
Data Source
AI summary
Systems and methods are disclosed for phase calibration between clock and data lanes at a data link receiver. In calibration mode, matching signals are transmitted over the clock and data lanes, and a phase offset is measured at the receiver. A phase shifter in one signal path is adjusted to a first phase to obtain a desired phase offset. For operation mode, the phase shifter is set based on the first phase. Embodiments measure phase offset using an XOR gate and use a phase interpolator as the phase shifter. Embodiments with multiple data lanes apply coarse calibration to a shared clock lane relative to a first data lane, and similar fine calibration to other data lanes. Calibration provides optimum signal-to-noise ratio or timing margin, enabling high transmission speeds at relatively low power. Variations are disclosed.