Receiver Clock Phase Detection Using Interpolated Signal Sampling

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Solution Overview

Problem

High-speed data transmission in receiver circuits faces challenges in accurately detecting phase deviations between data signals and sampling clocks, particularly due to variations in amplitude caused by transmission line losses, noise, and production or temperature variations, which can degrade detection accuracy and require specialized sampling circuits.

Innovation Solution

A receiver circuit that includes a sampling circuit to detect amplitude levels at specific timings, comparison circuits to interpolate an intermediate amplitude level, and a phase deviation detection circuit to correct phase deviations based on these comparisons, eliminating the need for a special sampling circuit at zero-crossing points and enhancing detection accuracy.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a special sampling circuit is used to detect amplitude level at zero-crossing point, then phase deviation detection accuracy is improved, but circuit size increases

Engineering Contradiction:
Improvephase deviation detection accuracyVSAvoidcircuit size
Core Design Contradiction:
Measurement precisionVSArea of stationary object

Solution Approach 1:

The patent creates a virtual copy of the zero-crossing amplitude level through interpolation calculation instead of physically sampling at the zero-crossing point. The interpolation circuit computes an intermediate amplitude level between two sampling points, effectively copying the function of a zero-crossing sampler without requiring dedicated hardware, thus reducing circuit size while maintaining detection accuracy

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The patent introduces an interpolation circuit as an intermediary between the sampling circuit and phase deviation detection circuit. This intermediary calculates the amplitude level at intermediate points (including zero-crossing points) based on sampled values, enabling accurate phase deviation detection without direct sampling at zero-crossing points, thereby eliminating the need for special sampling circuits

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If sampling is performed at zero-crossing point, then influence of amplitude variations is reduced, but detection complexity increases

Engineering Contradiction:
Improvedetection accuracyVSAvoiddetection complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent performs preliminary sampling at regular intervals before the actual phase deviation detection. By sampling at multiple points and pre-calculating intermediate amplitude levels through interpolation, the system prepares the necessary data in advance, making the subsequent phase deviation detection simpler and more accurate without requiring complex real-time processing at zero-crossing points

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8983014B2Receiver circuit and semiconductor integrated circuit
Publication Date: 2015.03.17 FUJITSU LTD
  • US8983014B2 patent drawing
  • US8983014B2 patent drawing
  • US8983014B2 patent drawing

AI summary

In a receiver circuit which can correct a deviation of phase between an input signal and a clock, a sampler detects an amplitude level of the input signal at timing indicated by the clock, a first comparison circuit compares a first and a second amplitude level detected by the sampler at first and second timings, respectively, with a determined threshold, an interpolation circuit calculates an intermediate level that approximates to an amplitude level of the input signal corresponding to an intermediate point between the first and second timings by an interpolation process based on the first and second amplitude levels, a second comparison circuit compares the intermediate level with the determined threshold, and a phase deviation detection circuit detects the deviation of phase between the clock and the input signal on the basis of comparison results obtained by the first and second comparison circuits.