Differential Signal Receiver Circuit for Spurious Pulse Rejection
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Solution Overview
Problem
Conventional isolated gate driver devices suffer from spurious pulses in the reconstructed signal due to common-mode ringing effects, which are not effectively mitigated by existing solutions that require costly and area-consuming isolation capacitors in the high-voltage die.
Innovation Solution
A receiver circuit with a logic circuit that corrects spurious pulses by detecting and discarding pulses exceeding a certain duration threshold, using asymmetric buffers and gating logic gates to produce corrected set and reset signals, thereby improving common-mode transient immunity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If isolation capacitors are placed in the high-voltage die to mitigate common-mode ringing, then common-mode transient immunity is improved, but device area and cost increase
Solution Approach 1:
The patent extracts the isolation capacitance function from the high-voltage die and relocates it to the low-voltage die. This allows the high-voltage die to be free of large capacitance elements while still achieving the necessary common-mode transient immunity through the same isolation capacitors positioned in the low-voltage section of the device.
Solution Approach 2:
The patent uses a copy of the isolation capacitor in the low-voltage die to perform the isolation function. Instead of placing physical capacitors in the high-voltage die, the system creates an electrical equivalent through the low-voltage isolation capacitors that replicates the desired isolation effect without requiring physical presence in the high-voltage section.
2Reliability
If isolation capacitors are placed in the high-voltage die to mitigate common-mode ringing, then common-mode transient immunity is improved, but device cost increases
Solution Approach 1:
The patent extracts the isolation capacitance function from the high-voltage die and relocates it to the low-voltage die. This allows the high-voltage die to be free of large capacitance elements while still achieving the necessary common-mode transient immunity through the same isolation capacitors positioned in the low-voltage section of the device.
Solution Approach 2:
The patent uses a copy of the isolation capacitor in the low-voltage die to perform the isolation function. Instead of placing physical capacitors in the high-voltage die, the system creates an electrical equivalent through the low-voltage isolation capacitors that replicates the desired isolation effect without requiring physical presence in the high-voltage section.
3Reliability
If conventional receiver circuits are used, then device complexity is low, but spurious pulses are not effectively rejected
Solution Approach 1:
The patent applies preliminary action by performing pulse width filtering on the differential signal before it is converted to a unipolar signal by the receiver. The filtering logic detects and removes spurious pulses that exceed a predetermined width threshold, preventing these erroneous pulses from affecting the output signal. This proactive approach to signal cleaning occurs in the differential domain before the critical signal conversion stage.
Data Source
AI summary
A receiver circuit receives a differential signal that includes positive and negative spikes, and produces an output signal as a function of the differential signal. A first comparator produces an intermediate set signal that includes a pulse at each positive spike of the differential signal, and a second comparator produces an intermediate reset signal that includes a pulse at each negative spike of the differential signal. A logic circuit detects whether the digital signal switches between a first value and a second value, and whether the intermediate reset signal and the intermediate set signal include pulses lasting longer than a threshold. The logic produces a set correction signal and a reset correction signal. The logic circuit produces a corrected set signal and a corrected reset signal. An output circuit produces an output signal based on the corrected set signal and the corrected reset signal.


