Receiver Reference Voltage and Clock Phase for SSN Cancellation
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Solution Overview
Problem
Simultaneous switching noise (SSN) causes signaling errors in integrated circuit receivers due to power supply disturbances, especially in systems using single-ended signaling, as it alters the data signal voltage levels, making it difficult for receivers to accurately determine logic levels.
Innovation Solution
The system adjusts the reference voltage and sampling clock phase in the receiver to mimic the noise and jitter induced by supply noise, using filters that replicate the impedance and jitter profiles of the power distribution network, based on the bus weight and number of switching bits, thereby canceling out the noise and jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple output drivers change state simultaneously at high speed to transmit multi-bit data, then data transmission speed is improved, but simultaneous switching noise is generated causing signaling errors
Solution Approach 1:
The system applies preliminary anti-action by predicting the SSN voltage disturbance before it occurs and pre-adjusting the reference voltage to counteract the expected noise. The receiver calculates the anticipated SSN based on known switching patterns and output driver states, then adjusts the reference voltage in advance to compensate for the upcoming noise, thereby preventing signaling errors before they can occur.
Solution Approach 2:
The system dynamically changes the reference voltage parameter in response to detected or predicted SSN conditions. By monitoring the power supply voltage and calculating the resulting SSN, the receiver adjusts the reference voltage level to match the noisy environment, maintaining adequate voltage margins for accurate logic level detection despite the simultaneous switching noise.
2Reliability
If reference voltage is adjusted to compensate for SSN, then signaling accuracy is improved, but system complexity increases due to dynamic adjustment mechanisms
Solution Approach 1:
The system implements feedback by continuously monitoring the power supply voltage and using this information to dynamically adjust the reference voltage. The receiver measures the actual voltage conditions, calculates the resulting SSN, and feeds this information back to the reference voltage adjustment mechanism, creating a closed-loop system that automatically compensates for noise without requiring complex external control.
Solution Approach 2:
The receiver performs self-service by autonomously calculating and adjusting its own reference voltage based on detected power supply conditions. The system uses its own monitoring capabilities to detect SSN, perform the necessary calculations, and adjust the reference voltage without requiring external intervention or complex additional circuitry, thereby reducing overall system complexity.
3Reliability
If sampling clock phase is adjusted to mimic jitter, then noise cancellation is improved, but device complexity increases due to phase adjustment circuitry
Solution Approach 1:
The system uses an intermediary approach by introducing a phase adjustment mechanism that acts as a mediator between the sampling clock and the noisy data signal. The phase adjustment circuitry serves as an intermediate element that modifies the clock phase to counteract jitter effects, thereby improving noise cancellation while isolating the complexity to a dedicated phase adjustment module rather than requiring complex changes throughout the entire sampling system.
Data Source
AI summary
A data signal is transmitted from a first circuit to a second circuit, with noise and/or jitter added to the data signal by supply noise in the power distribution network in the first circuit and/or a second circuit being effectively canceled out by adjustment of the reference voltage and/or the phase of the sampling clock used for sampling of the data signal in a manner that effectively mimics such noise and/or jitter added to the data signal. The second circuit uses a filter that has the impedance profile and/or the jitter profile of such power distribution network. The bus weight and/or the number of switching bits in the data pattern transmitted from the first circuit to the second circuit is applied to the filter to determine the adjustment to be made to the reference voltage or the phase of the sampling clock.