Digital Receiver Timestamping for Jitter Tolerance
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Solution Overview
Problem
Current digital receivers face degradation in performance due to timing jitter, leading to inaccurate clock recovery and bit errors, especially in burst mode digital transmission where a stable clock is difficult to establish.
Innovation Solution
A digital receiver that uses a sample and hold circuit with a counter to generate time stamps associated with input pulses, allowing a processor to recreate the input pulse train and determine transmitted values, thereby avoiding errors related to improper data slicing levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a clock recovery circuit is used to extract clock from the input signal, then the receiver can process continuous mode digital signals, but the timing jitter causes inaccurate clock recovery and bit errors
Solution Approach 1:
The invention extracts timing information from the input signal by detecting pulse arrival times and generating time stamps, separating this function from traditional clock recovery. The sample and hold circuit captures precise timing moments without requiring full clock synchronization, thereby avoiding jitter-induced clock recovery errors while maintaining continuous mode processing capability
Solution Approach 2:
The invention introduces time stamps as an intermediary representation of timing information. Instead of directly recovering the clock signal from a jittered input, the system uses time stamps to mark pulse arrival times, which then serve as the basis for signal reconstruction. This intermediary approach decouples the timing extraction from the problematic clock recovery process
2Measurement precision
If several bit periods are waited for clock stability, then accurate clock recovery is achieved, but burst mode digital transmission reception is delayed or difficult
Solution Approach 1:
The system performs preliminary timing measurements by continuously monitoring pulse arrival times and generating time stamps without waiting for clock stabilization. This preliminary action captures timing information immediately upon signal arrival, enabling burst mode reception to start without the usual delay while maintaining measurement precision through the time stamp mechanism
3Ease of operation
If a comparator with data slicing is used to determine sample values, then the digital signal can be processed, but timing jitter causes inaccurate slicing levels and bit errors
Solution Approach 1:
The invention replaces the mechanical comparator-based slicing system with a time-stamp-based reconstruction approach. Instead of using a comparator to slice the analog signal at fixed intervals (which is sensitive to timing jitter), the system uses precisely captured time stamps to determine when pulses occurred, reconstructing the digital signal based on timing information rather than amplitude slicing
Data Source
AI summary
A method, apparatus and system for improving the tolerance for timing jitter noise by eliminating the need to recover clock information from the input signal. There is no need to communicate clock synchronization information between transmit and receive gateways. In addition, the new receiving scheme can work in burst mode in its true sense, i.e., recovering data bits from the first incoming bit after an arbitrary period of time without transmitting.