Receiver Track Path Circuit for Die-to-Die Clock Phase Alignment
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Solution Overview
Problem
In integrated circuit (IC) die-to-die interfaces, clock synchronization is challenging due to unsynchronized local clock domains, leading to noise issues, power noise jitter, and mismatch problems exacerbated by voltage and temperature changes, requiring complex and costly circuit designs.
Innovation Solution
A cost-effective and simple circuit design is implemented using a tracking circuit with a receiver lane-to-lane skew calibration, incorporating a track path that mimics the clock phase of a data path to synchronize clocking, reducing power noise jitter and addressing voltage and temperature drift, with coarse and fine tune resolutions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a complex circuit design is used to achieve clock synchronization, then clock synchronization accuracy is improved, but device complexity and cost increase
Solution Approach 1:
The patent creates a track path that is substantially similar to the data path, copying its structural characteristics to mimic the clock phase. This allows the receiver to achieve accurate clock synchronization by tracking a replicated version of the data path rather than using complex synchronization circuits
Solution Approach 2:
The track path acts as an intermediary between the data path and the clock recovery mechanism. It receives a tracking clock signal and provides an adjusted version that mimics the clock phase of the data path, serving as a mediator that simplifies the overall synchronization architecture
2Measurement precision
If traditional clock synchronization methods are used, then clock phase alignment is achieved, but power noise jitter and temperature drift issues worsen
Solution Approach 1:
The track path implements a feedback mechanism where the tracking clock signal is continuously adjusted based on the phase relationship between the track path and data path. This feedback loop compensates for power noise jitter and temperature drift by dynamically adapting the clock phase alignment
Solution Approach 2:
The system transitions from static clock synchronization to dynamic tracking. The track path continuously adjusts the tracking clock signal phase in response to changing conditions, making the synchronization adaptive to temperature and power noise variations rather than fixed
3Speed
If high speed data transmission is implemented, then data rate is improved, but clock synchronization challenges and noise issues increase
Solution Approach 1:
By copying the data path structure into the track path, the system creates a reliable model that accurately reflects the timing characteristics even at high data rates. This allows the receiver to extract precise clock phase information necessary for high-speed transmission without proportionally increasing synchronization complexity
Solution Approach 2:
The track path performs preliminary clock phase adjustment before the main data recovery process. By pre-synchronizing the clock phase through the track path, the system prepares the receiver for high-speed data transmission, reducing the impact of noise and synchronization challenges during actual data reception
Data Source
AI summary
A circuit includes a first clock path configured to receive a first clock signal, and provide an adjusted version of the first clock signal with a first clock phase, a second clock path configured to receive a second clock signal, and provide an adjusted version of the second clock signal with a second clock phase related to the first clock phase, a data path configured to receive a data signal, and provide an adjusted version of the data signal with a third clock phase, and a track path configured to receive a third clock signal, and provide an adjusted version of the third clock signal with the first clock phase. The track path is substantially similar to the data path so as to mimic the third clock phase as the first clock phase.