Receiver Voltage Scaling Using Clock-to-Q Timing Feedback
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Solution Overview
Problem
High-speed data communications systems face significant power consumption challenges due to stringent timing requirements, where the DFE compensation value cannot be fully determined in time at high data rates, leading to inefficiencies in circuit operation and increased power usage.
Innovation Solution
A dynamic power control system that dynamically adjusts clock speeds and/or supply voltages to minimize power consumption by identifying critical paths and testing their operation, allowing for speculative DFE and voltage scaling to optimize power utilization while maintaining system performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If clock speed is increased to meet high data rate requirements, then data transmission speed is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic voltage scaling where the supply voltage to the receiver is adjusted in real-time based on measured communication link performance. When performance metrics indicate acceptable operation at lower voltages, the voltage is reduced, thereby lowering power consumption while maintaining data transmission speed. This dynamic adjustment resolves the contradiction by making the system adaptable rather than static.
Solution Approach 2:
The patent changes the electrical parameter (supply voltage) of the receiver based on measured performance metrics. By monitoring communication link performance and adjusting the voltage parameter accordingly, the system optimizes the trade-off between speed and power consumption, allowing operation at lower voltages when performance permits.
2Use of energy by moving object
If supply voltage is reduced to decrease power consumption, then energy efficiency is improved, but circuit timing performance deteriorates
Solution Approach 1:
The patent employs a feedback mechanism where communication link performance is continuously measured and used to control the voltage supply to the receiver. The performance metrics provide feedback that determines whether voltage reduction will compromise timing performance, allowing the system to maintain reliability while optimizing power consumption.
Solution Approach 2:
The patent performs preliminary measurement of communication link performance before adjusting voltage levels. By measuring performance metrics in advance and using them to determine appropriate voltage settings, the system ensures that voltage reduction will not cause timing failures, thus maintaining reliability while improving energy efficiency.
3Productivity
If speculative DFE is used to meet timing requirements at high data rates, then data rate capability is improved, but power consumption increases
Solution Approach 1:
The patent dynamically adjusts the voltage supply to the receiver based on measured performance, allowing the system to operate at lower voltages when speculative DFE is not needed. This dynamic control reduces power consumption while maintaining the ability to support high data rates when necessary, resolving the contradiction between productivity and energy use.
Data Source
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AI summary
Obtaining a periodic test signal, sampling the periodic test signal using a sampling element according to a sampling clock to generate a sampled periodic output, the sampling element operating according to a supply voltage provided by a voltage regulator, the voltage regulator providing the supply voltage according to a supply voltage control signal, comparing the sampled periodic output to the sampling clock to generate a clock-to-Q measurement indicative of a delay value associated with the generation of the sampled periodic output in response to the sampling clock, generating the supply voltage control signal based at least in part on an average of the clock-to-Q measurement, and providing the supply voltage to a data sampling element connected to the voltage regulator, the data sampling element being a replica of the sampling element, the data sampling element sampling a stream of input data according to the sampling clock.