Receiving Circuit Clock Recovery with DFE Phase Compensation
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Solution Overview
Problem
High-speed data transmission systems face challenges in clock and data recovery due to phase shifts caused by decision feedback equalization, leading to increased check error rates in receiving circuits.
Innovation Solution
A receiving circuit design that includes a sampling circuit, decision feedback equalizer, comparator circuits, phase detection, and phase adjustment mechanisms to synchronize clock signals and adjust phases based on calculated phase differences, ensuring optimal sampling phases and reducing check error rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If decision feedback equalization is performed on sampled data, then equalization effect is improved, but phase shift occurs causing check error rate to increase
Solution Approach 1:
The patent divides the equalization process into two separate stages: first performing equalization on center data sampled at the center of the data period, then performing equalization on boundary data sampled at the boundaries. This segmentation allows each equalization process to operate on optimally timed data without phase shift interference from the other, resolving the contradiction between achieving good equalization effect and maintaining low check error rate.
Solution Approach 2:
The patent introduces an intermediary mechanism - a phase adjustment circuit that calculates phase differences caused by equalization and compensates for them by adjusting the sampling clock phase. This intermediary component mediates between the equalization process and the sampling process, ensuring that the check error rate remains low even when strong equalization is applied.
2Device complexity
If single-phase sampling is used, then circuit complexity is reduced, but both equalization effect and phase accuracy deteriorate
Solution Approach 1:
The patent segments the sampling process into two distinct phases: center sampling for equalization and boundary sampling for phase detection. This segmentation allows each sampling operation to be optimized for its specific purpose, achieving high precision without requiring a completely complex multi-phase sampling system.
Solution Approach 2:
The patent performs preliminary equalization on center data before using boundary data for phase detection and further equalization. This preliminary action ensures that the data is properly equalized before the critical phase detection step, improving overall precision while maintaining relatively simple circuit architecture.
3Device complexity
If phase adjustment is performed without considering equalization-induced phase shift, then control complexity is reduced, but phase synchronization accuracy deteriorates
Solution Approach 1:
The patent implements a feedback mechanism where the phase difference caused by equalization is detected and used to adjust the sampling clock phase. The phase detection circuit monitors the boundary data and feeds back phase correction information to the clock generation circuit, creating a closed-loop system that automatically compensates for equalization-induced phase shifts.
Solution Approach 2:
The patent performs preliminary calculation of the phase difference that will be introduced by equalization, and applies compensation before the critical sampling operation. This preliminary phase compensation action ensures that phase synchronization accuracy is maintained without requiring complex real-time adjustment mechanisms.
Data Source
AI summary
A receiving circuit includes: a sampling circuit to sample input data in synchronization with first clock to obtain boundary data, and sample the input data in synchronization with second clock to obtain center data; a decision feedback equalizer to perform equalization on the center data using an equalization coefficient, and output first output data; a first comparator circuit to perform binary decision on the boundary data and output second output data; a phase detection circuit to detect phase information of the input data using the first output data and the second output data; a phase difference computation circuit to calculate phase difference of the first output data using the equalization coefficient; a first phase adjustment circuit to adjust phase of the first clock using the phase information; and a second phase adjustment circuit to adjust phase of the second clock using the phase information and the phase difference.