Receiving Circuit Clock Data Skew Reduction
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Solution Overview
Problem
Integrated circuits in semiconductor memory devices face errors in determining logic levels due to skew between input data and clock signals, as the clock pulse may not occur at the middle of the data input period, leading to incorrect discrimination of logic levels.
Innovation Solution
A receiving circuit is designed with a clock input portion that buffers a pattern signal and retards it to generate an input clock signal, and a data input portion that buffers another pattern signal to generate an input data signal, with a comparator adjusting the delay time to align the phases of the clock and data signals, thereby reducing skew and potential errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the clock pulse occurs at the middle of the data input period, then the receiving circuit can accurately discriminate logic levels with smaller errors, but this requires precise timing alignment between clock and data signals which is difficult to achieve due to skew
Solution Approach 1:
The patent applies preliminary action by measuring the phase difference between clock and data signals before actual data reception, and adjusting the delay time in advance to align the clock pulse with the middle of the data input period. This pre-adjustment ensures accurate logic level discrimination without timing errors during operation
Solution Approach 2:
The patent implements feedback by using a comparator to continuously monitor the phase relationship between clock and data signals, generating a comparison signal that feeds back to adjust the delay time. This closed-loop feedback mechanism maintains reliable timing alignment despite signal skew, ensuring consistent measurement precision
2Measurement precision
If delay adjustment mechanisms are added to align clock and data phases, then timing accuracy improves, but device complexity increases due to additional components
Solution Approach 1:
The patent changes the delay time parameter of the clock signal dynamically based on measured phase differences. By adjusting this single parameter through a controllable delay element rather than adding complex timing circuits, the patent achieves precise phase alignment with minimal increase in device complexity
Solution Approach 2:
The patent introduces a comparator as an intermediary element that measures phase difference and generates comparison signals to control the delay adjustment. This intermediary enables automatic phase alignment without requiring complex direct control mechanisms between clock and data paths
Data Source
AI summary
A receiving circuit includes a clock input portion configured to buffer a first pattern signal and configured to retard the buffered first pattern signal by a first delay time to generate an input clock signal, a data input portion configured to buffer a second pattern signal and configured to retard the buffered second pattern signal by a second delay time to generate an input data signal, and a comparator configured to compare a phase of the input clock signal with a phase of the input data signal to generate a comparison signal for adjusting the second delay time.