Receiving Device Equalization Circuit Reduces Inter-Symbol Interference

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Solution Overview

Problem

In communication systems, inter-symbol interference (ISI) caused by channel distortion leads to data misjudgment at the receiver, as the received signal is distorted, resulting in incorrect interpretation of data symbols.

Innovation Solution

A receiving device and signal conversion method that includes a first calculating circuit, error slicer, data slicer, second calculating circuit, and equalization circuit, which generate calculating signals, error signals, data signals, and feedback signals using equalization coefficients to reduce ISI by equalizing the received signal and generating a feedback signal that subtracts from the equalized signal to minimize post-cursor interference.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If equalization coefficients are introduced to reduce ISI, then data accuracy is improved, but device complexity increases

Engineering Contradiction:
Improvedata accuracyVSAvoiddevice complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent implements a feedback mechanism where the equalization circuit generates feedback signals based on the equalized signal and previously determined equalization coefficients. This feedback is fed back to the calculating circuit to generate updated coefficients, creating a closed-loop system that continuously refines the equalization to reduce ISI while adapting to channel conditions

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent dynamically adjusts equalization coefficients as parameters to optimize signal equalization. The calculating circuit determines multiple equalization coefficients based on the equalized signal and feedback signal, and the equalization circuit applies these coefficients to generate feedback signals. This parameter adjustment allows the system to adapt to changing channel conditions and reduce ISI effectively

Inventive Principle:
Principle #35Parameter changes

2Object-affected harmful factors

If multiple calculating circuits and equalization circuits are added to eliminate post-cursor interference, then inter-symbol interference is reduced, but the number of circuit components increases

Engineering Contradiction:
Improveinter-symbol interferenceVSAvoidnumber of circuit components
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The patent divides the equalization function into multiple segments handled by different circuits: a first calculating circuit that generates calculating signals, an equalization circuit that generates feedback signals using equalization coefficients, and a second calculating circuit that determines multiple equalization coefficients. This segmentation allows each circuit to specialize in specific aspects of the equalization process, making the overall system more manageable and efficient at reducing ISI

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces feedback signals as intermediaries between the equalization circuit and the calculating circuit. The feedback signal, generated by the equalization circuit based on the equalized signal and equalization coefficients, serves as an intermediary that carries information about the equalization effect back to the calculating circuit, enabling continuous optimization of the equalization process and reduction of post-cursor interference

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10079697B1Receiving device and signal conversion method
Publication Date: 2018.09.18 GLOBAL UNICHIP CORPORATION
  • US10079697B1 patent drawing
  • US10079697B1 patent drawing
  • US10079697B1 patent drawing

AI summary

A receiving device includes a first calculating circuit, an error slicer, a data slicer, a second calculating circuit, and an equalization circuit. The first calculating circuit is configured to generate a calculating signal according to an equalized signal and a feedback signal. The error slicer is configured to generate an error signal according to the calculating signal. The data slicer is configured to generate a data signal according to the calculating signal. The second calculating circuit is configured to generate a first, a second, and a third equalization coefficient according to the data signal and the error signal. The equalization circuit is configured to generate the feedback signal according to the first, the second, and the third equalization coefficient. A gain value of the equalization circuit is associated with the first equalization coefficient. A time constant of the equalization circuit is associated with the second and the third equalization coefficient.