Receiving Device Signal Alignment Circuit
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Solution Overview
Problem
Existing receiving devices and memory systems face challenges in properly aligning received data signals, leading to increased circuit area and power consumption due to significant bit pattern deviations, which are not effectively addressed by current technologies.
Innovation Solution
A receiving device with a first and second sampling circuit, a control circuit, and an output circuit that aligns data signals by selecting binary data based on phase shift directions of clock signals, ensuring proper synchronization and reducing bit pattern deviations upstream of deserializers to minimize circuit area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If data signals are processed without proper alignment, then bit pattern deviations occur, but circuit area and power consumption increase
Solution Approach 1:
The patent applies preliminary action by performing signal alignment processing before deserialization. The receiving device aligns data signals from multiple lanes upstream of the deserializers, preventing bit pattern deviations from propagating through the system. This early intervention reduces the need for additional correction circuits downstream, thereby reducing overall circuit area while maintaining signal integrity.
2Manufacturing precision
If data signals are processed without proper alignment, then bit pattern deviations occur, but power consumption increases
Solution Approach 1:
The patent performs signal alignment upstream before deserialization, preventing bit pattern deviations that would require additional power-consuming correction processing downstream. By addressing alignment issues early in the signal path, the system avoids the need for extensive error correction and reprocessing, thereby reducing overall power consumption.
3Manufacturing precision
If multiple sampling circuits are used to align data signals, then signal alignment improves, but device complexity increases
Solution Approach 1:
The patent segments the signal alignment function across multiple sampling circuits that operate in parallel on different data lanes. Each sampling circuit handles a specific lane, and their outputs are combined after alignment. This segmentation allows precise alignment of each lane independently while distributing the complexity across modular units, making the overall system more manageable and efficient.
Solution Approach 2:
The sampling circuits are designed with multi-functionality, serving both as alignment mechanisms and as data extraction units. By making the sampling circuits universal components that perform multiple functions (alignment, sampling, and lane-specific processing), the patent reduces the need for separate dedicated alignment circuits, thereby reducing overall device complexity while maintaining alignment precision.
Data Source
AI summary
A receiving device includes a first sampling circuit extracting first binary data from a first signal based on a first edge timing of a first clock signal. The receiving device includes a second sampling circuit extracting second binary data from the first signal based on the first edge timing, and further extracting third binary data from the first signal based on a second edge timing of a second clock signal having a phase delayed from a phase of the first clock signal. The receiving device includes a circuit outputting a second signal indicating a phase shift direction of a third clock signal. The receiving device includes a circuit outputting waveform data based on the first binary data and the second binary data or the third binary data. The second sampling circuit selects either the second binary data or the third binary data based on the second signal.