Reception Circuit Timing Adjustment for DDR Memory
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Solution Overview
Problem
Relative timing differences between the internal clock signal and the data strobe signal in semiconductor devices, such as DDR memory, cause errors in read data due to variations in operation voltage and temperature changes, hindering high-speed data transfer.
Innovation Solution
A reception circuit comprising a control signal generation circuit, asynchronous transfer circuits, a pattern data generation circuit, a determination circuit, and a set value calculation circuit, which adjusts the timing of the data strobe signal relative to the internal clock signal by generating enable signals, latching data, and calculating transfer set values to compensate for latency and phase differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transfer speed is increased to achieve high-speed operation, then productivity is improved, but timing errors between internal clock signal and data strobe signal occur due to voltage and temperature variations, causing data errors
Solution Approach 1:
The patent applies preliminary action by performing timing adjustment before data transfer occurs. The reception circuit adjusts the timing of the data strobe signal relative to the internal clock signal in advance, compensating for anticipated voltage and temperature variations. This pre-adjustment ensures that even at high transfer speeds, the timing relationship remains accurate, preventing data errors before they can occur.
Solution Approach 2:
The patent implements feedback by continuously monitoring the timing relationship between the data strobe signal and internal clock signal, and automatically adjusting the timing offset based on detected deviations. The reception circuit measures actual timing differences caused by voltage and temperature changes, then feeds this information back to adjust the phase alignment, ensuring sustained data accuracy during high-speed operation.
2Reliability
If timing adjustment circuitry is added to compensate for voltage and temperature variations, then data accuracy is improved, but device complexity increases
Solution Approach 1:
The patent uses an intermediary approach by introducing a reception circuit that acts as a mediator between the data strobe signal and the internal clock signal. This reception circuit contains timing adjustment functionality that processes the data strobe signal and aligns it with the internal clock signal, compensating for voltage and temperature variations without requiring complex modifications to the core processing circuits.
Solution Approach 2:
The patent applies parameter changes by dynamically adjusting the timing offset parameter between the data strobe signal and internal clock signal based on detected voltage and temperature conditions. The reception circuit modifies phase relationships and timing parameters in real-time, allowing accurate data reception across varying operating conditions without fundamentally changing the architecture of the memory or processor circuits.
Data Source
AI summary
A reception circuit includes a control signal generation circuit that generates a first enable signal based on a strobe signal and a second enable signal based on a core clock signal and a pointer control signal. A pattern data generation circuit generates determination pattern data from the first enable signal. An asynchronous transfer circuit latches the determination pattern data based on the first enable signal and the strobe signal and outputs determination data corresponding to the latched determination pattern data based on the second enable signal and the core clock signal. A determination circuit determines a timing for generating the pointer control signal based on the determination data. A set value calculation circuit calculates a transfer set value based on the determination result of the determination circuit. The control signal generation circuit updates the pointer control signal based on the transfer set value.