Reception Clock Phase Control for High-Speed Jitter Tolerance
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Solution Overview
Problem
High-speed serial data reception circuits face challenges in maintaining jitter tolerance due to variations in current supplied to current controlled oscillators, leading to shifts in lock points of phase lock circuits, which deteriorate performance as communication speeds increase.
Innovation Solution
A semiconductor device with a current controlled oscillation circuit and a dual-switching circuit configuration that controls current supply to match the number of output signals from first and second circuits, ensuring equal phase adjustments on both the UP and DOWN sides, thereby stabilizing the oscillation clock phase.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If communication speed of transfer of reception data is increased, then data transmission rate is improved, but jitter tolerance characteristics deteriorate due to increased influence of current variation
Solution Approach 1:
The invention changes the control parameter from direct current magnitude control to phase-based control. The phase lock circuit controls the phase of the oscillation clock to match the phase of reception data, rather than directly controlling current magnitude. This parameter transformation eliminates the direct relationship between current variation and lock point shift, maintaining jitter tolerance at high communication speeds.
Solution Approach 2:
The invention implements a feedback mechanism where the phase lock circuit continuously monitors the phase difference between the oscillation clock and reception data, and adjusts the current controlled oscillation circuit accordingly. This feedback loop ensures that phase alignment is maintained despite current variations, preserving jitter tolerance characteristics even as communication speed increases.
2Ease of operation
If current supplied to current controlled oscillator is varied to control phase, then phase adjustment capability is improved, but lock point shifts due to current variation
Solution Approach 1:
The phase lock circuit provides continuous feedback to monitor and correct lock point shifts. By detecting phase differences between the oscillation clock and reception data, the system dynamically adjusts the current controlled oscillation circuit to maintain stable locking, preventing drift caused by current variations while preserving phase adjustment capability.
Solution Approach 2:
The invention transforms the control approach from direct current magnitude control to phase-based control. Instead of varying current to directly achieve phase adjustment (which causes lock point shifts), the system controls the phase of the oscillation clock to match the reception data phase, separating phase adjustment from current variation effects and stabilizing the lock point.
3Measurement precision
If phase lock circuit controls current to adjust oscillation clock phase, then phase synchronization is improved, but setup and hold time differences increase
Solution Approach 1:
The invention changes the control parameter from current magnitude to phase alignment. By controlling the phase of the oscillation clock to match the phase of reception data rather than directly controlling current magnitude, the system achieves phase synchronization without creating imbalances in setup and hold times, as phase-based control inherently maintains symmetrical timing characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves jitter tolerance by ensuring balanced phase changes, eliminating differences in setup and hold times and enhancing the overall performance of high-speed data reception systems.
Implementation Method 1
a current controlled oscillation circuit that generates an oscillation clock in response to a current supplied
Data Source
AI summary
A semiconductor device has a current controlled oscillation circuit configured to generate an oscillation clock in response to a current supplied, a first circuit configured to output a first signal when a phase of the oscillation clock is later than a phase of reception data, and to output a second signal when a phase of the oscillation clock is earlier than a phase of the reception data, and a current control circuit configured to control a current to be supplied to the current controlled oscillation circuit such that the number of times of output of the first signal from the first circuit matches the number of times of output of the second signal from the first circuit.