Reception Clock Synchronization for High-Resolution Signal Sampling

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Solution Overview

Problem

In real-time networks, the mismatch between the signal clock frequency of the transmitting subscriber and the counter clock frequency of the receiving subscriber leads to limited resolution and synchronization issues, resulting in quantization errors and jitter, which are exacerbated by the cascading effects of clock synchronization.

Innovation Solution

A method where the reception clock of the receiving subscriber is derived from the counter clock, with its phase position adapted to match the signal clock, using a phase-locked loop to ensure synchronization and adjust the reception clock frequency to a multiple of the counter clock frequency, allowing for higher resolution sampling with reduced quantization errors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the counter clock frequency is increased to improve sampling resolution, then the resolution of signal sampling is improved, but the device complexity and power consumption increase significantly

Engineering Contradiction:
Improvesampling resolutionVSAvoidcounter clock frequency requirements
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent divides the high-frequency sampling task into two stages: a first counter operating at a lower frequency for coarse time measurement, and a second counter operating at a higher frequency for fine time measurement. This segmentation allows the system to achieve high sampling resolution without requiring the entire system to operate at high frequency, thereby reducing overall device complexity and power consumption while maintaining measurement precision.

Inventive Principle:
Principle #1Segmentation

2Adaptability or versatility

If asynchronous clock frequencies are used at transmitting and receiving subscribers, then flexibility in clock frequency selection is improved, but synchronization accuracy and signal reconstruction quality deteriorate

Engineering Contradiction:
Improveclock frequency selection flexibilityVSAvoidsignal sampling accuracy
Core Design Contradiction:
Adaptability or versatilityVSMeasurement precision

Solution Approach 1:

The patent implements a feedback mechanism where the receiving subscriber measures the actual arrival time of signal samples using its second counter and compares this with the expected arrival time based on the transmitting subscriber's timestamp. This feedback information is used to calculate and apply a compensation value that corrects for clock frequency mismatches, thereby maintaining high sampling accuracy despite using asynchronous and flexible clock frequencies at different subscribers.

Inventive Principle:
Principle #23Feedback

3Device complexity

If the second counter operates at a fixed clock frequency to simplify design, then device complexity is reduced, but the ability to adapt to different signal rates and achieve optimal sampling is limited

Engineering Contradiction:
Improvecounter configuration flexibilityVSAvoidsignal rate adaptation capability
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The patent makes the second counter's clock frequency dynamic rather than fixed. The second counter can be configured to operate at different clock frequencies depending on the signal rate being received and the desired sampling resolution. This dynamic configuration allows the system to adapt to various signal rates and optimize sampling performance while maintaining a relatively simple base design structure.

Inventive Principle:
Principle #15Dynamics

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables improved resolution and synchronization of the received signal, reducing quantization errors and jitter, and allows for higher bit rates without being directly dependent on the counter clock frequency, effectively addressing the limitations of existing synchronization methods.

Implementation Method 1

A method where the reception clock of the receiving subscriber is derived from the counter clock, with its phase position adapted to match the signal clock, using a phase-locked loop to ensure synchronization

Methodology Applied
Scientific EffectPhase-locked loop:

Data Source

PatentUS11956343B2High resolution signal reception
Publication Date: 2024.04.09 ABB (SCHWEIZ) AG
  • US11956343B2 patent drawing
  • US11956343B2 patent drawing

AI summary

A method for reception of a signal by a subscriber of a real-time network. The signal includes a signal clock having a signal clock frequency and the subscriber includes a counter, which has a counter clock with a counter clock frequency and which maps a local time of the subscriber. The method includes sampling the signal with a reception clock of a reception counter of the subscriber, the reception clock being derived from the counter clock, whereby the reception counter maps the local time of the subscriber, adapting a phase position of the reception clock to a phase position of the signal clock when said reception clock is derived from the counter clock, and sampling the signal at a reception clock frequency of the reception counter.