Reception Device Clock Generation with Phase Fluctuation Removal
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Solution Overview
Problem
Existing reception devices in passive optical networks (PON) systems face challenges in generating a synchronous clock signal with high frequency stability due to frequency fluctuations in the reception data signal, which affects the reliability of clock signals used for data reproduction and transmission.
Innovation Solution
The reception device employs a clock/data reproduction unit and a synchronous clock generation unit that utilize a multi-phase local clock signal to generate a reception clock signal, with phase setting circuits and timing signal generation circuits to adjust the phase of the clock signal based on comparisons with the reception data signal, thereby separating frequency and phase fluctuations and improving frequency stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a clock signal is reproduced directly from the reception data signal, then the clock signal is synchronized with the reception data signal, but the frequency stability is poor due to frequency fluctuations in the reception data signal
Solution Approach 1:
The patent segments the clock signal generation process into two independent parts: a stable local clock source that provides frequency reference, and a phase adjustment mechanism that synchronizes with the reception data signal. This separation allows the frequency stability to be maintained from the local clock source while only the phase needs to track the reception signal, thereby resolving the contradiction between synchronization and frequency stability.
Solution Approach 2:
The patent introduces a phase adjustment circuit as an intermediary between the local clock source and the data reproduction unit. This intermediary component handles the phase synchronization function independently, allowing the main clock source to maintain its frequency stability while the intermediary adjusts phase timing to match the reception data signal, thus resolving the contradiction.
2Measurement precision
If the phase of the clock signal is continuously adjusted to match the reception data signal, then synchronization is improved, but frequency fluctuations are transferred to the clock signal
Solution Approach 1:
The patent divides the clock signal functions into frequency generation (handled by stable local clock source) and phase adjustment (handled by separate phase adjustment circuit). This segmentation ensures that phase synchronization accuracy is improved through the dedicated phase adjustment mechanism while the frequency stability is preserved by the independent local clock source that does not follow reception signal fluctuations.
Solution Approach 2:
The patent implements dynamic phase adjustment where only the phase component of the clock signal is dynamically adapted to match the reception data signal timing, while the frequency component remains static and stable. This dynamic separation allows precise phase synchronization without transferring frequency fluctuations, resolving the contradiction between measurement precision and reliability.
3Reliability
If a simple clock reproduction method is used, then the device complexity is low, but the frequency stability of the generated clock signal is insufficient
Solution Approach 1:
The patent employs a local clock source that serves itself as the frequency reference, independent of the reception data signal. This self-service approach provides inherent frequency stability without requiring complex external reference systems. Combined with a relatively simple phase adjustment circuit, this achieves high frequency stability with moderate device complexity, resolving the contradiction.
Solution Approach 2:
The patent changes the operational parameters of the clock generation by using a local clock source with predetermined stable frequency instead of directly deriving clock from the fluctuating reception signal. This parameter change (using stable local frequency reference) improves frequency stability while the phase adjustment mechanism adds only minimal complexity, effectively resolving the contradiction between reliability and device complexity.
Data Source
AI summary
A first phase setting circuit generates a first phase setting signal. A first synchronous signal generator generates a first synchronous clock signal having a phase set by the first phase setting signal from a multi-phase local clock signal. By removing a phase fluctuation component representing phase fluctuation of the reception data signal from a first signal including a frequency component representing a frequency offset between a multi-phase local clock signal and a reception data signal and the phase fluctuation component, a second generation unit generates a second signal including the frequency component. The first phase setting circuit updates the first phase setting signal according to the second signal.