Recess Array Device Gate Oxide Thickness Profile
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Solution Overview
Problem
Prior recess array devices in the semiconductor industry face issues with high gate-induced drain leakage (GIDL) currents due to band-to-band tunneling effects in the overlap region between the gate and drain, which can be mitigated by increasing gate oxide thickness but compromises write back performance.
Innovation Solution
A recess array device with a gate trench featuring a bump portion and a gate oxide layer of varying thicknesses, where the oxide layer is thicker on the sidewalls and thinner on the top portion of the bump, reducing GIDL currents while maintaining write back performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the gate oxide layer thickness is increased to reduce GIDL currents, then the harmful effect of band-to-band tunneling is mitigated, but the write back performance is compromised
Solution Approach 1:
The gate oxide layer is designed with non-uniform thickness: thicker at the sidewalls (first thickness) to reduce GIDL currents, and thinner at the top portion of the bump (third thickness) to maintain write back performance. This local variation in oxide thickness allows each region to optimize for its specific functional requirement.
Solution Approach 2:
The invention introduces a vertical dimension to the gate oxide thickness profile by creating a bump structure with varying heights. The oxide thickness is controlled to be greater at lower elevations (sidewalls) and progressively thinner at higher elevations (top of bump), effectively using the vertical dimension to resolve the contradiction between GIDL reduction and write back performance.
2Productivity
If the cell density is increased to improve memory capacity, then the integration level is enhanced, but the GIDL current problem becomes more significant
Solution Approach 1:
The gate oxide thickness is locally optimized within each memory cell structure to reduce GIDL currents while maintaining the high cell density required for large memory capacity. The thicker oxide at sidewalls specifically targets GIDL reduction in the overlap region without affecting the overall cell dimensions.
Solution Approach 2:
The invention changes the physical parameter of gate oxide thickness from a uniform value to a spatially varying parameter, with different thicknesses at different locations within the gate trench. This parameter variation allows the device to achieve both high density and reduced GIDL effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces GIDL currents by optimizing gate oxide layer thickness, thereby enhancing the operational performance and retention time of thin-oxide cell devices without compromising write back performance.
Implementation Method 1
GIDL current in the overlap region may be caused by band to band tunneling effects
Data Source
AI summary
A recess array device includes a semiconductor substrate and at least an active area in a main surface of the semiconductor substrate. A gate trench penetrates through the active area. The gate trench includes a first sidewall, a second sidewall facing the first sidewall, and a bottom surface extending between the first and the second sidewalls. A bump portion is disposed in the gate trench. The bump portion has two opposite sidewalls and a top portion extending between the two opposite sidewalls. A gate oxide layer is formed in the gate trench. The gate oxide layer has a first thickness on the first and second sidewalls, a second thickness on the two opposite sidewalls of the bump portion, and a third thickness on the top portion of the bump portion. The first thickness is greater than the second thickness. The second thickness is greater than the third thickness.