Recess Channel Array Transistor Fabrication
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Solution Overview
Problem
Semiconductor devices, such as DRAMs, face challenges in preventing short channel effects and source/drain punch-through, leading to increased leakage current and reduced refresh time, which are not effectively addressed by existing technologies.
Innovation Solution
The use of recess channel array transistors with a first gate electrode partially filling a trench and source and drain regions, along with a bit line extending over the drain region and a contact plug connecting it, improves the reliability and performance by minimizing step differences and enhancing electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If recess channel array transistors are used to reduce channel length and address short channel effects, then device performance is improved, but step differences between regions cause errors and reduced reliability
Solution Approach 1:
The patent introduces a multi-level trench structure with different depths (first trench and second trench) to accommodate different transistor types. By utilizing vertical dimensionality and creating stepped trench configurations, the invention resolves the step difference problem between recess channel array transistors and planar transistors while maintaining both device performance and reliability
Solution Approach 2:
The patent segments the transistor structure into different regions: recess channel array transistors with gates in first trenches, and planar transistors with gates in second trenches. This segmentation allows each transistor type to be optimized independently while coexisting in the same semiconductor device, addressing both performance and reliability requirements
2Speed
If channel length is reduced to improve device performance, then speed is improved, but short channel effects and source/drain punch-through increase
Solution Approach 1:
The patent applies different structural configurations to different regions: recess channel array transistors with partially filled trenches for high-speed performance, and planar transistors with fully filled trenches for stable electrical characteristics. This local quality differentiation allows short channel effects to be managed while maintaining high speed in critical regions
3Stability of the object's composition
If recess channel array transistors are used to address punch-through, then electrical stability is improved, but leakage current increases and refresh time is reduced
Solution Approach 1:
The patent creates a dynamic balance between different transistor types: recess channel array transistors provide electrical stability and punch-through prevention, while planar transistors compensate for leakage current issues. The combination allows the system to maintain electrical stability while managing energy loss through complementary transistor characteristics
Data Source
AI summary
A method of fabricating a semiconductor device using a recess channel array is disclosed. A substrate is provided having a first region and a second region, including a first transistor in the first region including a first gate electrode partially filling a trench, and source and drain regions that are formed at both sides of the trench, and covered by a first insulating layer. A first conductive layer is formed on the substrate. A contact hole through which the drain region is exposed is formed by patterning the first conductive layer and the first insulating layer. A contact plug is formed that fills the contact hole. A bit line is formed that is electrically connected to the drain region through the contact plug, and simultaneously a second gate electrode is formed in the second region by patterning the first conductive layer.