Recess Channel Floating Gate Memory Cell Integration
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Solution Overview
Problem
The integration of 1.5 T ESF3 memory with logic processes is complicated due to the higher stack topology of gate structures with floating gates, making it difficult to control the structure topology and increase the coupling ratio and effective channel length.
Innovation Solution
The implementation of recess channel floating gate memory cells with a common source coupling source side injection programming method, which omits control gates and simplifies the integration with logic processes by enhancing the coupling ratio and effective channel length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If control gates are included in floating gate memory cells, then the memory cell can be programmed and erased, but the structure topology becomes more complex and integration with logic processes becomes complicated
Solution Approach 1:
The patent extracts and removes the control gate from the floating gate memory cell structure, retaining only the essential floating gate component. This simplification maintains the core programming capability through source side injection while eliminating the complexity introduced by control gates, directly resolving the contradiction between programming reliability and structural simplicity
Solution Approach 2:
The patent employs a simplified floating gate structure that can be easily formed and integrated without the need for complex control gate structures. This approach uses a more manufacturable, simpler structure that achieves the desired memory functionality without the overhead of control gates
2Reliability
If the channel length is increased to reduce short channel effect, then the effective channel length increases, but the area occupied by the memory cell increases
Solution Approach 1:
The patent applies local quality by creating a recess channel structure where the channel region has different geometric properties than the surrounding areas. The recessed channel provides enhanced electrostatic control and effective length extension localized to the channel region, achieving improved short channel effect control without proportionally increasing the overall memory cell footprint
Solution Approach 2:
The patent transitions from a planar channel structure to a recessed channel structure by introducing a vertical dimension. This dimensional change allows the channel to extend deeper into the substrate, effectively increasing the channel length and improving short channel control while maintaining a compact planar footprint
3Productivity
If the coupling ratio is increased to improve programming efficiency, then the programming speed increases, but the structure becomes more complex requiring additional components
Solution Approach 1:
The patent employs source side injection programming where the source itself serves as the injection terminal, eliminating the need for separate control gates or additional programming structures. The source region directly injects carriers into the floating gate through the tunnel oxide, achieving efficient programming through a self-service mechanism that simplifies the overall structure
Data Source
AI summary
A semiconductor device includes a substrate and a floating gate memory cell. The floating gate memory cell includes an erase gate structure disposed on the substrate, a first floating gate structure, a second floating gate structure, a first word line, a common source, a second word line, a first spacer and a second spacer. The first floating gate structure and the second floating gate structure are recessed in the substrate at two opposite sides of the erase gate structure. The first word line and the second word line are respectively adjacent to the first floating gate structure and the second floating gate structure. The common source is disposed in the substrate under the erase gate structure. The first spacer and the second spacer are respectively disposed between the first floating gate structure and the first word line and between the second floating gate structure and the second word line.