Recess Gate Interconnect Structure With Air Gaps for Lower DRAM Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices, such as DRAM, are scaled down, parasitic capacitance between adjacent memory cells increases, limiting operation speeds due to reduced space between cells.
Innovation Solution
A semiconductor device design featuring a recess gate structure with a conductive pillar and landing pad configuration, surrounded by a dielectric layer, which includes air gaps to reduce parasitic capacitance by using materials with lower dielectric constants.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If semiconductor devices are scaled down to reduce size, then device density and integration are improved, but parasitic capacitance between adjacent memory cells increases
Solution Approach 1:
The patent extracts the harmful dielectric material from the space between adjacent conductive pillars and replaces it with air gaps. By removing the solid dielectric material that causes parasitic capacitance and substituting it with air (which has a dielectric constant of approximately 1), the parasitic capacitance between adjacent memory cells is significantly reduced while maintaining the scaled-down device dimensions.
Solution Approach 2:
The patent introduces a porous structure in the form of air gaps between adjacent conductive pillars. These air gaps create a low-dielectric-constant region that reduces parasitic capacitance. The porous structure is formed by selective removal of dielectric material, creating voids that fill with air during processing, thereby achieving low parasitic capacitance in the scaled-down device architecture.
2Quantity of substance
If space between adjacent memory cells is reduced, then device density is improved, but operation speed is limited due to increased parasitic capacitance
Solution Approach 1:
The patent removes the solid dielectric material from between adjacent conductive pillars and replaces it with air gaps. This extraction of harmful material reduces parasitic capacitance, which directly improves the RC time constant and enables faster operation speeds while maintaining high device density achieved through scaling.
Solution Approach 2:
The patent changes the dielectric parameter (dielectric constant) of the material between conductive pillars from a high value (solid dielectric) to a low value (air with dielectric constant ≈1). This parameter change reduces parasitic capacitance and RC delay, thereby improving operation speed while maintaining the high density configuration.
3Ease of manufacture
If conventional dielectric materials are used between conductive pillars, then manufacturing simplicity is maintained, but parasitic capacitance and RC delay are high
Solution Approach 1:
The patent extracts the solid dielectric material from specific regions between conductive pillars while leaving dielectric material in other regions. This selective removal creates air gaps that reduce parasitic capacitance without significantly complicating the manufacturing process, as the air gaps are formed through standard lithography and etching techniques followed by air exposure during subsequent processing steps.
Data Source
AI summary
The present application provides a semiconductor device and a method for preparing the same. The semiconductor device includes a substrate having an active region; a recess gate structure disposed in the substrate and intersecting the active region; a conductive pillar disposed over the substrate and electrically connected to the active region; a landing pad disposed on the conductive pillar and electrically connected to the conductive pillar; and a stack of dielectric layers disposed over the substrate and laterally surrounding the conductive pillar and the landing pad. The semiconductor device also includes a contact structure disposed between the substrate and the conductive pillar, a capacitor plug disposed on the landing pad and electrically connected to the landing pad, and a storage capacitor disposed on the capacitor plug and electrically connected to the capacitor plug.