Recess Gate Structure Asymmetric Insulation for GIDL Reduction
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Solution Overview
Problem
Semiconductor devices with reduced channel length suffer from short channel effects and gate-induced drain leakage (GIDL), which are exacerbated by increased gate resistance and leakage current, necessitating a solution to improve refresh characteristics.
Innovation Solution
A recess gate structure is formed with asymmetrical insulation film thicknesses at the edges of gate patterns, where the thickness is greater over the storage node contact plug than the bit line contact plug, to reduce GIDL and enhance leakage current refresh characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If channel length is reduced to increase integration density, then productivity and integration density are improved, but short channel effects and gate induced drain leakage occur worsening device reliability
Solution Approach 1:
The patent applies local quality by forming a thicker gate insulation film specifically at the overlap region between the gate electrode and source/drain regions where GIDL occurs, while maintaining a thinner film in other regions. This localized thickening suppresses leakage current at the critical area without unnecessarily increasing gate resistance or affecting other device regions.
Solution Approach 2:
The patent implements asymmetry by creating an asymmetric gate insulation film structure where the film thickness varies across different regions of the gate. The insulation film is thicker at the overlap region compared to non-overlap regions, creating an asymmetric thickness profile that specifically addresses GIDL at the overlap area while maintaining optimal characteristics elsewhere.
2Reliability
If gate channel length is increased to prevent short channel effects, then device reliability is improved, but gate resistance increases and manufacturing complexity increases
Solution Approach 1:
Instead of uniformly increasing gate channel length, the patent applies local quality by selectively thickening the gate insulation film only at the overlap region. This localized approach prevents short channel effects and GIDL at the critical overlap area without requiring an overall increase in gate channel length, thereby avoiding increased gate resistance and manufacturing complexity.
3Reliability
If gate insulation film is thickly deposited in overlap region to reduce GIDL, then leakage current is reduced improving refresh characteristics, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies preliminary action by first forming a preliminary gate insulation film across the entire gate region, then performing selective thinning or additional deposition only at the overlap region. This staged approach allows precise control of the final thickness distribution, ensuring the thicker film is formed only where needed while maintaining manufacturing feasibility.
Solution Approach 2:
The gate insulation film formation process is segmented into multiple steps: first forming a base insulation film uniformly, then selectively modifying the thickness at the overlap region through targeted deposition or removal. This segmentation of the film formation process enables precise thickness control at different gate regions, achieving the desired asymmetric thickness profile with controlled manufacturing precision.
Data Source
AI summary
A semiconductor device and a method for manufacturing the same are disclosed. A recess gate structure is formed between an overlapping region between a gate and a source/drain so as to suppress increase in gate induced drain leakage (GIDL), and a gate insulation film is more thickly deposited in a region having weak GIDL, thereby reducing GIDL and thus improving refresh characteristics due to leakage current.