Recess Gate Fin Transistor for Memory Driver Signal Boosting
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Solution Overview
Problem
As memory devices grow larger, effectively driving larger arrays of memory cells without signal degradation becomes technically challenging, particularly in scaling sub-wordline driver circuits to maintain consistent signal delivery across increasing memory cells.
Innovation Solution
The use of transistors with a wider effective gate width, formed by re-purposing semiconductor fins and parallel wordlines, allows for improved signal boosting in sub-wordline driver circuits, enabling efficient operation at higher voltages and smaller form factors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory arrays are scaled up to larger sizes, then storage capacity increases, but signal degradation occurs and driving capability decreases
Solution Approach 1:
The patent changes the physical parameters of the transistor by forming a wider effective gate width using re-purposed semiconductor fins and parallel wordlines. This parameter change increases the drive strength and signal boosting capability, enabling reliable signal delivery across larger memory arrays without degradation.
Solution Approach 2:
The patent applies multi-functionality by re-purposing existing semiconductor fins and parallel wordlines that originally served structural and address line functions to also form the gate structure of driver transistors. This universal use of components enables signal boosting capability while maintaining the original memory array functionality.
2Power
If transistor gate width is increased to improve signal boosting, then driving capability improves, but device area increases
Solution Approach 1:
The patent resolves this contradiction by making the semiconductor fins and wordlines serve multiple functions: they form the gate structure of the transistor (providing signal boosting) while also maintaining their original roles as structural elements and address lines. This eliminates the need for additional dedicated gate structures that would increase area.
Solution Approach 2:
The patent merges the gate structure with existing memory array components (semiconductor fins and wordlines), combining the driving function with the storage structure. This integration allows the same physical structures to provide both signal boosting and memory cell organization without requiring separate dedicated components.
3Area of moving object
If memory device form factor is reduced, then integration density increases, but signal delivery effectiveness decreases
Solution Approach 1:
The patent changes the transistor gate width parameter by utilizing the spacing and dimensions of re-purposed fins and wordlines. This creates a wider effective gate that provides sufficient signal boosting capability even in compact form factors, maintaining signal delivery effectiveness while enabling smaller device size through higher integration density.
Data Source
AI summary
Apparatus and methods are disclosed, including transistors, semiconductor devices and systems. Example semiconductor devices and methods include transistors formed from a plurality of semiconductor fins, and using a number of conductive lines passing through trenches between the fins to serve as a gate for the transistor.