Mixed Recess Gate Peripheral Circuits for Smaller 3D Memory
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Solution Overview
Problem
The challenge in 3D memory devices is to reduce the size of peripheral circuits without sacrificing performance, as the increasing number of page buffers dominates chip area and channel leakage degradation limits device area shrinkage.
Innovation Solution
Incorporating a mix of recess gate transistors and flat gate transistors in peripheral circuits, where recess gate transistors are used in page buffers to shrink device size while maintaining performance, and flat gate transistors are used in other circuits to reduce fabrication complexity and variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If recess gate transistors are used in peripheral circuits, then device size is reduced, but fabrication complexity increases
Solution Approach 1:
The patent applies different transistor structures to different functional blocks: recess gate transistors are used specifically in page buffer circuits where size reduction is critical, while flat gate transistors are used in other peripheral circuits where fabrication simplicity is more important. This localized application resolves the contradiction by optimizing each block according to its specific requirements rather than uniformly applying one structure throughout.
2Area of moving object
If device area is shrunk, then chip size is reduced, but channel leakage degradation occurs
Solution Approach 1:
The patent changes the structural parameters of the transistor gate by introducing a recess configuration that extends into the substrate. This parameter change allows the gate to maintain better control over the channel even as the overall device area is reduced, thereby suppressing channel leakage while achieving area shrinkage. The recess depth and gate electrode dimensions are specifically optimized to balance area reduction with leakage control.
Data Source
AI summary
In certain aspects, a semiconductor device includes a substrate and a first transistor. The first transistor includes a first well in the substrate and having a recess, a recess gate structure including a protrusion structure, and a first source and a first drain spaced apart by the recess gate structure. The protrusion structure extends into the recess of the first well. The recess gate structure includes a first gate dielectric and a first gate electrode on the first gate dielectric.