Recess Gate MOSFET Structure Using Metallic Insertion Layers

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The challenge in semiconductor device manufacturing lies in scaling down MOSFETs with recess gate structures, where high concentration doping for source and drain regions becomes difficult due to increased external parasitic resistance and defects, limiting device miniaturization and on-current performance.

Innovation Solution

A semiconductor device with a recess gate structure that incorporates a metallic insertion layer between the gate insulating and capping layers, which increases effective doping concentration through a charge-plasma effect, enhancing on-current without high concentration doping, and reduces variations between devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If high concentration doping is applied to source and drain regions to reduce external parasitic resistance, then on-state current performance improves, but device miniaturization becomes difficult due to increased process difficulty and defects

Engineering Contradiction:
Improveon-state current performanceVSAvoidprocess difficulty for source and drain formation
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

A metallic insertion layer is introduced as an intermediary component between the source/drain regions and the gate structure. This metallic layer serves as a mediator that reduces external parasitic resistance without requiring high concentration doping of the semiconductor source/drain regions, thereby improving on-state current performance while avoiding the manufacturing difficulties and defects associated with high concentration doping processes

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The invention changes the approach from modifying semiconductor material parameters (doping concentration) to introducing a new material parameter (metallic layer with high conductivity). By substituting the doping-based resistance reduction method with a metallic insertion layer, the patent achieves low external parasitic resistance without the need for high concentration doping, thus resolving the contradiction between performance improvement and manufacturing ease

Inventive Principle:
Principle #35Parameter changes

2Object-affected harmful factors

If high concentration doping is used to reduce external parasitic resistance, then contact resistance decreases, but device scaling becomes limited due to solubility and diffusivity limits of dopants

Engineering Contradiction:
Improveexternal parasitic resistanceVSAvoiddevice size for scaling
Core Design Contradiction:
Object-affected harmful factorsVSLength of moving object

Solution Approach 1:

The metallic insertion layer acts as an intermediary that provides a low-resistance path for current flow between the source/drain contacts and the gate. This mediator approach eliminates the need to push dopant concentration to its physical limits, enabling continued device scaling without being constrained by dopant solubility and diffusivity boundaries

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The invention transitions from changing semiconductor doping parameters to introducing a metallic layer with inherently high electrical conductivity. This parameter change allows for continued device miniaturization since the metallic layer's conductivity is not limited by semiconductor dopant physical constraints, thus resolving the contradiction between reducing parasitic resistance and enabling device scaling

Inventive Principle:
Principle #35Parameter changes

3Reliability

If high concentration doping is applied to increase effective doping concentration, then on-current increases, but defects and inter-device variation increase requiring additional heat treatment

Engineering Contradiction:
Improveon-currentVSAvoidinter-device variation
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The metallic insertion layer serves as an intermediary that enhances on-current through its high conductivity without introducing the defects and variations associated with high concentration doping. By mediating the current flow path, the metallic layer improves on-current while maintaining uniformity across devices, eliminating the need for additional heat treatment to correct doping-induced variations

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The invention changes from modifying semiconductor doping parameters to introducing a metallic layer with controlled physical and chemical properties. This parameter change enables high on-current while maintaining manufacturing precision, as the metallic layer can be deposited with uniform thickness and composition across the wafer, avoiding the inter-device variations that plague high concentration doping processes

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively increases on-current and maintains operational characteristics at low doping concentrations, overcoming scaling limitations and reducing defects, while allowing for device miniaturization and improved performance at lower applied voltages.

Implementation Method 1

the metallic insertion layer is configured to increase an effective doping concentration of the semiconductor region by changing an energy band of the source or the drain region

Methodology Applied
Scientific EffectCharge-plasma effect:

Data Source

PatentUS20240274713A1Semiconductor device including recess gate structure and method of manufacturing the same
Publication Date: 2024.08.15 SK HYNIX INC
  • US20240274713A1 patent drawing
  • US20240274713A1 patent drawing
  • US20240274713A1 patent drawing

AI summary

A semiconductor device and a method of manufacturing the same. The semiconductor device has a substrate in which recess regions are formed and semiconductor regions acting as a source region or a drain region is defined between the recess regions; a gate insulating layer disposed on an inner surface of each recess region; a recess gate disposed on the gate insulating layer in each recess region; an insulating capping layer disposed above the recess gate in each recess region; a metallic insertion layer disposed between a side surface of the recess gate and a side surface of the insulating capping layer and facing with a side surface of the source region or the drain region; and an intermediate insulating layer disposed between the metallic insertion layer and the recess gate to electrically insulate the metallic insertion layer from the recess gate.